cal_block_v1_4_1.rtl Architecture Reference

RocketIO calibration module. More...

Inheritance diagram for cal_block_v1_4_1.rtl:

[legend]

Collaboration diagram for cal_block_v1_4_1.rtl:

[legend]

List of all members.

Functions
string	ExtendString ( string_in: in string , string_len: in integer )
	extend string
boolean	StringToBool ( S: in string )
	cast string to bool
Processes
PROCESS_2	( DCLK , RESET )
	Sync Reset.
PROCESS_3	( DCLK )
	User Data Input.
PROCESS_4	( DCLK )
	User DRP Address.
PROCESS_5	( DCLK )
	User Data Write Enable.
PROCESS_6	( DCLK )
PROCESS_7	( DCLK )
PROCESS_8	( DCLK )
	User Data Output.
PROCESS_9	( DCLK )
	User Data Ready.
PROCESS_10	( DCLK )
	Active signal to indicate a Calibration Block operation.
PROCESS_11	( DCLK )
PROCESS_12	( DCLK )
PROCESS_13	( DCLK )
PROCESS_14	( DCLK )
PROCESS_15	( DCLK )
PROCESS_16	( DCLK )
	GT Data Ready.
PROCESS_17	( DCLK )
	Calibration Block (CB) FSM reset.
PROCESS_18	( cb_state , sd_req , user_req , gt_drdy_r )
	Calibration Block (CB) FSM.
PROCESS_19	( DCLK )
	Signal Detect Request for DRP operation.
PROCESS_20	( DCLK )
	Indicates Signal Detect DRP Read.
PROCESS_21	( DCLK )
	Indicates Signal Detect DRP Write.
PROCESS_22	( DCLK )
	Signal Detect DRP Write Working Register.
PROCESS_23	( sd_state )
	Generate DRP Addresses for Signal Detect.
PROCESS_24	( DCLK )
	Assert when Signal Detect DRP Operation is Complete.
PROCESS_25	( DCLK )
PROCESS_26	( DCLK )
PROCESS_27	( sd_state , RX_SIGNAL_DETECT , sd_drp_done )
PROCESS_28	( DCLK )
	DRP Read/Write FSM reset.
PROCESS_29	( drp_state , drp_rd , drp_wr , gt_drdy_r )
	DRP Read/Write FSM.
Constants
C_DRP_DWIDTH	integer := 16
C_DRP_AWIDTH	integer := 8
C_RESET	std_logic_vector ( 3 downto 0 ) := " 0001 "
C_IDLE	std_logic_vector ( 3 downto 0 ) := " 0010 "
C_SD_DRP_OP	std_logic_vector ( 3 downto 0 ) := " 0100 "
C_USER_DRP_OP	std_logic_vector ( 3 downto 0 ) := " 1000 "
C_DRP_IDLE	std_logic_vector ( 4 downto 0 ) := " 00001 "
C_DRP_READ	std_logic_vector ( 4 downto 0 ) := " 00010 "
C_DRP_WRITE	std_logic_vector ( 4 downto 0 ) := " 00100 "
C_DRP_WAIT	std_logic_vector ( 4 downto 0 ) := " 01000 "
C_DRP_COMPLETE	std_logic_vector ( 4 downto 0 ) := " 10000 "
C_SD_IDLE	std_logic_vector ( 13 downto 0 ) := " 00000000000001 "
C_SD_RD_PT_ON	std_logic_vector ( 13 downto 0 ) := " 00000000000010 "
C_SD_MD_PT_ON	std_logic_vector ( 13 downto 0 ) := " 00000000000100 "
C_SD_WR_PT_ON	std_logic_vector ( 13 downto 0 ) := " 00000000001000 "
C_SD_RD_RXDIGRX_ON	std_logic_vector ( 13 downto 0 ) := " 00000000010000 "
C_SD_MD_RXDIGRX_ON	std_logic_vector ( 13 downto 0 ) := " 00000000100000 "
C_SD_WR_RXDIGRX_ON	std_logic_vector ( 13 downto 0 ) := " 00000001000000 "
C_SD_WAIT	std_logic_vector ( 13 downto 0 ) := " 00000010000000 "
C_SD_RD_RXDIGRX_RESTORE	std_logic_vector ( 13 downto 0 ) := " 00000100000000 "
C_SD_MD_RXDIGRX_RESTORE	std_logic_vector ( 13 downto 0 ) := " 00001000000000 "
C_SD_WR_RXDIGRX_RESTORE	std_logic_vector ( 13 downto 0 ) := " 00010000000000 "
C_SD_RD_PT_OFF	std_logic_vector ( 13 downto 0 ) := " 00100000000000 "
C_SD_MD_PT_OFF	std_logic_vector ( 13 downto 0 ) := " 01000000000000 "
C_SD_WR_PT_OFF	std_logic_vector ( 13 downto 0 ) := " 10000000000000 "
C_MGTA_RX_DIGRX_ADDR	std_logic_vector ( 7 downto 0 ) := " 01111101 "
C_MGTA_TX_PT_ADDR	std_logic_vector ( 7 downto 0 ) := " 01001100 "
C_MGTB_RX_DIGRX_ADDR	std_logic_vector ( 7 downto 0 ) := " 01011001 "
C_MGTB_TX_PT_ADDR	std_logic_vector ( 7 downto 0 ) := " 01001110 "
Signals
reset_r	std_logic_vector ( 1 downto 0 )
user_di_r	std_logic_vector ( C_DRP_DWIDTH-1 downto 0 ) := ( others = > ' 0 ' )
user_daddr_r	std_logic_vector ( C_DRP_AWIDTH-3 downto 0 )
user_den_r	std_logic
user_req	std_logic
user_dwe_r	std_logic
user_drdy_i	std_logic
gt_drdy_r	std_logic := ' 0 '
gt_do_r	std_logic_vector ( C_DRP_DWIDTH-1 downto 0 ) := ( others = > ' 0 ' )
rxdigrx_cache	std_logic
txpost_tap_pd_cache	std_logic
gt_do_r_sel	std_logic_vector ( 2 downto 0 )
gt_daddr_sel	std_logic_vector ( 2 downto 0 )
c_rx_digrx_addr	std_logic_vector ( C_DRP_AWIDTH-1 downto 0 )
c_tx_pt_addr	std_logic_vector ( C_DRP_AWIDTH-1 downto 0 )
c_txpost_tap_pd_bin	std_logic
c_rxdigrx_bin	std_logic
user_sel	std_logic
sd_sel	std_logic
sd_req	std_logic := ' 0 '
sd_read	std_logic := ' 0 '
sd_write	std_logic := ' 0 '
sd_drp_done	std_logic := ' 0 '
sd_wr_wreg	std_logic_vector ( C_DRP_DWIDTH-1 downto 0 ) := ( others = > ' 0 ' )
sd_addr_r	std_logic_vector ( C_DRP_AWIDTH-3 downto 0 )
drp_rd	std_logic
drp_wr	std_logic
cb_state	std_logic_vector ( 3 downto 0 )
cb_next_state	std_logic_vector ( 3 downto 0 )
drp_state	std_logic_vector ( 4 downto 0 )
drp_next_state	std_logic_vector ( 4 downto 0 )
sd_state	std_logic_vector ( 13 downto 0 )
sd_next_state	std_logic_vector ( 13 downto 0 )

---

Detailed Description

RocketIO calibration module.

created by RocketIO wizard

Definition at line 143 of file cal_block_v1_4_1.vhd.

---

Member Function Documentation

[Function]

string ExtendString		( string_in in string ,
		string_len in integer )

extend string

Definition at line 149 of file cal_block_v1_4_1.vhd.

  function ExtendString (string_in  : string;
                         string_len : integer) 
    return string is
    variable string_out : string(1 to string_len) := (others => ' ');

  begin
    if string_in'length > string_len then
      string_out := string_in(1 to string_len);
    else
      string_out(1 to string_in'length) := string_in;
    end if;
    return string_out;
  end ExtendString;

[Process]

PROCESS_10

( DCLK )

Active signal to indicate a Calibration Block operation.

Definition at line 411 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then
      if (cb_state = C_RESET) then
        ACTIVE <= '0';
      else
        if ((not (cb_state = C_IDLE)) and
            (not (cb_state = C_USER_DRP_OP))) then
          ACTIVE <= '1';
        else
          ACTIVE <= '0';
        end if;
      end if;
    end if;
  end process;

[Process]

PROCESS_11

( DCLK )

Storing the value of RXDIGRX. The value is written from the default parameter upon reset or when the user writes to DRP register in those bits location.

Definition at line 430 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then
      if (reset_r(0) = '1') then
        rxdigrx_cache <= c_rxdigrx_bin;
      elsif ((drp_state = C_DRP_WRITE) and
             (cb_state = C_USER_DRP_OP) and
             (user_daddr_r(5 downto 0) = c_rx_digrx_addr(5 downto 0))) then
        rxdigrx_cache <= user_di_r(1);
      end if;
    end if;
  end process;

[Process]

PROCESS_12

( DCLK )

Storing the value of TXPOST_TAP_PD. The value is written from the default parameter upon reset or when the user writes to DRP register in those bits location.

Definition at line 446 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then
      if (reset_r(0) = '1') then
        txpost_tap_pd_cache <= c_txpost_tap_pd_bin;
      elsif ((drp_state = C_DRP_WRITE) and
             (cb_state = C_USER_DRP_OP) and
             (user_daddr_r(5 downto 0) = c_tx_pt_addr(5 downto 0))) then
        txpost_tap_pd_cache <= user_di_r(12);
      end if;
    end if;
  end process;

[Process]

PROCESS_13

( DCLK )

GT Data Output: the data output is generated either from a Signal Detect FSM operation or a user access.

Definition at line 465 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then

      if (gt_do_r_sel(2) = '1') then
        gt_do_r <= sd_wr_wreg;
      elsif (gt_do_r_sel = "001") then
        gt_do_r <= user_di_r;
      else
        null;
      end if;

    end if;
  end process;

[Process]

PROCESS_14

( DCLK )

GT DRP Address: the DRP address is generated either from a Signal Detect FSM operation, or a user access. DRP address ranges from 0x40 to 0x7F.

Definition at line 485 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then

      if (gt_daddr_sel(2) = '1') then
        GT_DADDR(5 downto 0) <= sd_addr_r(5 downto 0);
      elsif (gt_daddr_sel = "001") then
        GT_DADDR(5 downto 0) <= user_daddr_r(5 downto 0);
      else
        null;
      end if;

      GT_DADDR(7 downto 6) <= "01";

    end if;
  end process;

[Process]

PROCESS_15

( DCLK )

GT Data Enable: the data enable is generated whenever there is a DRP Read or a DRP Write

Definition at line 504 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then
      if (reset_r(0) = '1') then
        GT_DEN <= '0';
      else
        if ((drp_state = C_DRP_IDLE) and
            ((drp_wr = '1') or (drp_rd = '1'))) then
          GT_DEN <= '1';
        else
          GT_DEN <= '0';
        end if;
      end if;
    end if;
  end process;

[Process]

PROCESS_16

( DCLK )

GT Data Ready.

Definition at line 524 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then
      gt_drdy_r <= GT_DRDY;
    end if;
  end process;

[Process]

PROCESS_17

( DCLK )

Calibration Block (CB) FSM reset.

Definition at line 540 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then
      if (reset_r(0) = '1') then
        cb_state <= C_RESET;
      else
        cb_state <= cb_next_state;
      end if;
    end if;
  end process;

[Process]

PROCESS_18		( cb_state ,
		sd_req ,
		user_req ,
		gt_drdy_r )

Calibration Block (CB) FSM.

Definition at line 552 of file cal_block_v1_4_1.vhd.

  process (cb_state, sd_req, user_req, gt_drdy_r)
    variable cb_fsm_name : string(1 to 25);
  begin
    case cb_state is

      when C_RESET =>

        cb_next_state <= C_IDLE;
        cb_fsm_name   := ExtendString("C_RESET", 25);

      when C_IDLE =>

        if (sd_req = '1') then
          cb_next_state <= C_SD_DRP_OP;
        elsif (user_req = '1') then
          cb_next_state <= C_USER_DRP_OP;
        else
          cb_next_state <= C_IDLE;
        end if;

        cb_fsm_name := ExtendString("C_IDLE", 25);

      when C_SD_DRP_OP =>

        if (gt_drdy_r = '1') then
          cb_next_state <= C_IDLE;
        else
          cb_next_state <= C_SD_DRP_OP;
        end if;

        cb_fsm_name := ExtendString("C_SD_DRP_OP", 25);

      when C_USER_DRP_OP =>

        if (gt_drdy_r = '1') then
          cb_next_state <= C_IDLE;
        else
          cb_next_state <= C_USER_DRP_OP;
        end if;

        cb_fsm_name := ExtendString("C_USER_DRP_OP", 25);

      when others =>

        cb_next_state <= C_IDLE;
        cb_fsm_name   := ExtendString("default", 25);

    end case;
  end process;

[Process]

PROCESS_19

( DCLK )

Signal Detect Request for DRP operation.

Definition at line 606 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then
      if ((sd_state = C_SD_IDLE) or (sd_drp_done = '1')) then
        sd_req <= '0';
      else
        sd_req <= sd_read or sd_write;
      end if;
    end if;
  end process;

[Process]

PROCESS_2		( DCLK ,
		RESET )

Sync Reset.

Definition at line 302 of file cal_block_v1_4_1.vhd.

  process (DCLK, RESET)
  begin
    if (RESET = '1') then
      reset_r <= "11";
    elsif (rising_edge(DCLK)) then
      reset_r <= '0' & reset_r(1);
    end if;
  end process;

[Process]

PROCESS_20

( DCLK )

Indicates Signal Detect DRP Read.

Definition at line 618 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then
      if ((sd_state = C_SD_IDLE) or (sd_drp_done = '1')) then
        sd_read <= '0';
      else
        if ((sd_state = C_SD_RD_PT_ON) or
            (sd_state = C_SD_RD_RXDIGRX_ON) or
            (sd_state = C_SD_RD_RXDIGRX_RESTORE) or
            (sd_state = C_SD_RD_PT_OFF)) then  
          sd_read <= '1';
        else
          sd_read <= '0';
        end if;
      end if;
    end if;
  end process;

[Process]

PROCESS_21

( DCLK )

Indicates Signal Detect DRP Write.

Definition at line 637 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then
      if ((sd_state = C_SD_IDLE) or (sd_drp_done = '1')) then
        sd_write <= '0';
      else
        if ((sd_state = C_SD_WR_PT_ON) or
            (sd_state = C_SD_WR_RXDIGRX_ON) or
            (sd_state = C_SD_WR_RXDIGRX_RESTORE) or
            (sd_state = C_SD_WR_PT_OFF)) then  
          sd_write <= '1';
        else
          sd_write <= '0';
        end if;
      end if;
    end if;
  end process;

[Process]

PROCESS_22

( DCLK )

Signal Detect DRP Write Working Register.

Definition at line 656 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then
      if ((cb_state = C_SD_DRP_OP) and (sd_read = '1') and (GT_DRDY = '1')) then
        sd_wr_wreg <= GT_DI;
      else
        case sd_state is

          when C_SD_MD_PT_ON =>
            sd_wr_wreg <= sd_wr_wreg(15 downto 13) & '0' &
                          sd_wr_wreg(11 downto 0);
          when C_SD_MD_RXDIGRX_ON =>
            sd_wr_wreg <= sd_wr_wreg(15 downto 2) & '1' & sd_wr_wreg(0);
          when C_SD_MD_RXDIGRX_RESTORE =>
            sd_wr_wreg <= sd_wr_wreg(15 downto 2) & rxdigrx_cache &
                          sd_wr_wreg(0);
          when C_SD_MD_PT_OFF =>
            sd_wr_wreg <= sd_wr_wreg(15 downto 13) & txpost_tap_pd_cache &
                          sd_wr_wreg(11 downto 0);
          when others =>
            null;
        end case;
      end if;
    end if;
  end process;

[Process]

PROCESS_23

( sd_state )

Generate DRP Addresses for Signal Detect.

Definition at line 683 of file cal_block_v1_4_1.vhd.

  process (sd_state)
  begin
    case sd_state is
      when C_SD_RD_PT_ON =>
        sd_addr_r(5 downto 0) <= c_tx_pt_addr(5 downto 0);
      when C_SD_WR_PT_ON =>
        sd_addr_r(5 downto 0) <= c_tx_pt_addr(5 downto 0);
      when C_SD_RD_PT_OFF =>
        sd_addr_r(5 downto 0) <= c_tx_pt_addr(5 downto 0);
      when C_SD_WR_PT_OFF =>
        sd_addr_r(5 downto 0) <= c_tx_pt_addr(5 downto 0);
      when C_SD_RD_RXDIGRX_ON =>
        sd_addr_r(5 downto 0) <= c_rx_digrx_addr(5 downto 0);
      when C_SD_WR_RXDIGRX_ON =>
        sd_addr_r(5 downto 0) <= c_rx_digrx_addr(5 downto 0);
      when C_SD_RD_RXDIGRX_RESTORE =>
        sd_addr_r(5 downto 0) <= c_rx_digrx_addr(5 downto 0);
      when C_SD_WR_RXDIGRX_RESTORE =>
        sd_addr_r(5 downto 0) <= c_rx_digrx_addr(5 downto 0);
      when others =>
        sd_addr_r(5 downto 0) <= c_tx_pt_addr(5 downto 0);
    end case;
  end process;

[Process]

PROCESS_24

( DCLK )

Assert when Signal Detect DRP Operation is Complete.

Definition at line 708 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then
      if ((GT_DRDY = '1') and (cb_state = C_SD_DRP_OP)) then
        sd_drp_done <= '1';
      else
        sd_drp_done <= '0';
      end if;
    end if;
  end process;

[Process]

PROCESS_25

( DCLK )

GT_LOOPBACK, GT_TXENC8B10BUSE and GT_TXBYPASS8B10B Switch the GT11 to serial loopback mode and enable 8B10B when the Signal Detect is Low.

Definition at line 722 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then
      if (reset_r(0) = '1') then
        GT_LOOPBACK <= "00";
      elsif (RX_SIGNAL_DETECT = '0') then
        GT_LOOPBACK <= "11";
      else
        GT_LOOPBACK <= USER_LOOPBACK;
      end if;
    end if;
  end process;

[Process]

PROCESS_26

( DCLK )

Signal Detect Block FSM: The SD FSM is triggered when RX_SIGNAL_DETECT goes Low

Definition at line 743 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then
      if (reset_r(0) = '1') then
        sd_state <= C_SD_IDLE;
      else
        sd_state <= sd_next_state;
      end if;
    end if;
  end process;

[Process]

PROCESS_28

( DCLK )

DRP Read/Write FSM reset.

Definition at line 901 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then
      if (reset_r(0) = '1') then
        drp_state <= C_DRP_IDLE;
      else
        drp_state <= drp_next_state;
      end if;
    end if;
  end process;

[Process]

PROCESS_29		( drp_state ,
		drp_rd ,
		drp_wr ,
		gt_drdy_r )

DRP Read/Write FSM.

Definition at line 913 of file cal_block_v1_4_1.vhd.

  process (drp_state, drp_rd, drp_wr, gt_drdy_r)
    variable drp_fsm_name : string(1 to 25);
  begin
    case drp_state is
      when C_DRP_IDLE =>

        if (drp_wr = '1') then
          drp_next_state <= C_DRP_WRITE;
        else
          if (drp_rd = '1') then
            drp_next_state <= C_DRP_READ;
          else
            drp_next_state <= C_DRP_IDLE;
          end if;
        end if;

        drp_fsm_name := ExtendString("C_DRP_IDLE", 25);

      when C_DRP_READ =>

        drp_next_state <= C_DRP_WAIT;
        drp_fsm_name   := ExtendString("C_DRP_READ", 25);

      when C_DRP_WRITE =>

        drp_next_state <= C_DRP_WAIT;
        drp_fsm_name   := ExtendString("C_DRP_WRITE", 25);

      when C_DRP_WAIT =>

        if (gt_drdy_r = '1') then
          drp_next_state <= C_DRP_COMPLETE;
        else
          drp_next_state <= C_DRP_WAIT;
        end if;

        drp_fsm_name := ExtendString("C_DRP_WAIT", 25);

      when C_DRP_COMPLETE =>

        drp_next_state <= C_DRP_IDLE;
        drp_fsm_name   := ExtendString("C_DRP_COMPLETE", 25);

      when others =>
        drp_next_state <= C_DRP_IDLE;
        drp_fsm_name   := ExtendString("default", 25);

    end case;
  end process;

[Process]

PROCESS_3

( DCLK )

User Data Input.

Definition at line 315 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then
      if (USER_DEN = '1') then
        user_di_r <= USER_DI;
      end if;
    end if;
  end process;

[Process]

PROCESS_4

( DCLK )

User DRP Address.

Definition at line 325 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then
      if (USER_DEN = '1') then
        user_daddr_r <= USER_DADDR(C_DRP_AWIDTH-3 downto 0);
      end if;
    end if;
  end process;

[Process]

PROCESS_5

( DCLK )

User Data Write Enable.

Definition at line 335 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then
      if (reset_r(0) = '1') then
        user_dwe_r <= '0';
      elsif (USER_DEN = '1') then
        user_dwe_r <= USER_DWE;
      end if;
    end if;
  end process;

[Process]

PROCESS_6

( DCLK )

Register the user_den_r when the user is granted access from the Arbitration FSM

Definition at line 348 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then
      if ((reset_r(0) = '1') or
          (cb_state = C_USER_DRP_OP) or
          ((USER_DADDR(7) = '1') or (USER_DADDR(6) = '0'))) then
        user_den_r <= '0';
      elsif (user_den_r = '0') then
        user_den_r <= USER_DEN;
      end if;
    end if;
  end process;

[Process]

PROCESS_7

( DCLK )

Generate the user request (user_req) signal when the user is not accessing the same DRP addresses as the Calibration Block or when the Calibration Block is in idle, reset, or wait states.

Definition at line 364 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then
      if ((reset_r(0) = '1') or (cb_state = C_USER_DRP_OP)) then

        user_req <= '0';

      elsif (
        (not(user_daddr_r(5 downto 0) = c_rx_digrx_addr(5 downto 0))) and
        (not(user_daddr_r(5 downto 0) = c_tx_pt_addr(5 downto 0)))
        ) then

        user_req <= user_den_r;

      elsif ((sd_state = C_SD_IDLE) or (sd_state = C_SD_WAIT)) then

        user_req <= user_den_r;

      end if;
    end if;
  end process;

[Process]

PROCESS_8

( DCLK )

User Data Output.

Definition at line 387 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then
      if ((cb_state = C_USER_DRP_OP) and (GT_DRDY = '1')) then
        USER_DO <= GT_DI;
      end if;
    end if;
  end process;

[Process]

PROCESS_9

( DCLK )

User Data Ready.

Definition at line 397 of file cal_block_v1_4_1.vhd.

  process (DCLK)
  begin
    if (rising_edge(DCLK)) then
      if ((reset_r(0) = '1') or (user_drdy_i = '1')) then
        user_drdy_i <= '0';
      elsif (cb_state = C_USER_DRP_OP) then
        user_drdy_i <= GT_DRDY;
      end if;
    end if;
  end process;

[Function]

boolean StringToBool

( S in string )

cast string to bool

Definition at line 164 of file cal_block_v1_4_1.vhd.

  function StringToBool (S : string) return boolean is
  begin
    if (ExtendString(S, 5) = "TRUE ") then
      return true;
    elsif (ExtendString(S, 5) = "FALSE") then
      return false;
    else
      return false;
    end if;
  end function StringToBool;

---

The documentation for this class was generated from the following file:

• cal_block_v1_4_1.vhd