ddr_chksum_adder Entity Reference
32-bit DSP adder More...
Inheritance diagram for ddr_chksum_adder:
Collaboration diagram for ddr_chksum_adder:
Architectures | |
| BEHAVIORAL | Architecture |
| 32-bit DSP adder More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| unisim | |
| Library with Xilinx primitives. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| numeric_std | |
| arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
| Vcomponents | |
Ports | |
| AB_IN | in std_logic_vector ( 31 downto 0 ) |
| CARRYIN_IN | in std_logic |
| CEA_IN | in std_logic |
| CEB_IN | in std_logic |
| CECINSUB_IN | in std_logic |
| CEC_IN | in std_logic |
| CEM_IN | in std_logic |
| CEP_IN | in std_logic |
| CLK_IN | in std_logic |
| C_IN | in std_logic_vector ( 31 downto 0 ) |
| RSTA_IN | in std_logic |
| RSTB_IN | in std_logic |
| RSTCARRYIN_IN | in std_logic |
| RSTC_IN | in std_logic |
| RSTM_IN | in std_logic |
| RSTP_IN | in std_logic |
| BCOUT_OUT | out std_logic_vector ( 17 downto 0 ) |
| PCOUT_OUT | out std_logic_vector ( 47 downto 0 ) |
| P_OUT | out std_logic_vector ( 47 downto 0 ) |
Detailed Description
32-bit DSP adderDefinition at line 56 of file ddr_chksum_adder.vhd.
Member Data Documentation
ieee library [Library] |
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 50 of file ddr_chksum_adder.vhd.
std_logic_1164 package [Package] |
unisim library [Library] |
The documentation for this class was generated from the following file:
