prescaler Entity Reference

Simple Prescaler. More...

Inheritance diagram for prescaler:

Inheritance graph
[legend]
Collaboration diagram for prescaler:

Collaboration graph
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List of all members.


Architectures

prescaler_arc Architecture
 Simple Prescaler. More...

Libraries

ieee 
 standard IEEE library

Packages

std_logic_1164 
 std_logic definitions, see file
std_logic_arith 
 arithmetic operations on std_logic datatypes, see file
std_logic_unsigned 
 unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file

Generics

divider  integer range 0 to 127 := 10

Ports

CLK  in std_logic
 Clock Input.
CE  in std_logic
 Clock Enable.
R  in std_logic
 Reset.
TC  out std_logic
 Clock Output.


Detailed Description

Simple Prescaler.

Definition at line 34 of file prescaler.vhd.


Member Data Documentation

CE in std_logic [Port]

Clock Enable.

Definition at line 37 of file prescaler.vhd.

CLK in std_logic [Port]

Clock Input.

Definition at line 36 of file prescaler.vhd.

ieee library [Library]

standard IEEE library

Reimplemented in main_components.

Definition at line 25 of file prescaler.vhd.

R in std_logic [Port]

Reset.

Definition at line 38 of file prescaler.vhd.

std_logic_1164 package [Package]

std_logic definitions, see file

Reimplemented in main_components.

Definition at line 27 of file prescaler.vhd.

std_logic_arith package [Package]

arithmetic operations on std_logic datatypes, see file

Definition at line 29 of file prescaler.vhd.

std_logic_unsigned package [Package]

unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file

Definition at line 31 of file prescaler.vhd.

TC out std_logic [Port]

Clock Output.

Definition at line 39 of file prescaler.vhd.


The documentation for this class was generated from the following file:

Author: M.Niegl
Generated on Tue Nov 4 00:58:14 2008 for BCM-AAA by doxygen 1.5.7.1-20081012