Architectures | |
prescaler_arc | Architecture |
Simple Prescaler. More... | |
Libraries | |
ieee | |
standard IEEE library | |
Packages | |
std_logic_1164 | |
std_logic definitions, see file | |
std_logic_arith | |
arithmetic operations on std_logic datatypes, see file | |
std_logic_unsigned | |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
Generics | |
divider | integer range 0 to 127 := 10 |
Ports | |
CLK | in std_logic |
Clock Input. | |
CE | in std_logic |
Clock Enable. | |
R | in std_logic |
Reset. | |
TC | out std_logic |
Clock Output. |
Definition at line 34 of file prescaler.vhd.
CE in std_logic [Port] |
CLK in std_logic [Port] |
ieee library [Library] |
standard IEEE library
Reimplemented in main_components.
Definition at line 25 of file prescaler.vhd.
R in std_logic [Port] |
std_logic_1164 package [Package] |
std_logic definitions, see file
Reimplemented in main_components.
Definition at line 27 of file prescaler.vhd.
std_logic_arith package [Package] |
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 31 of file prescaler.vhd.
TC out std_logic [Port] |