statistics Entity Reference

Determines minimum, maximum and average of a series of input values. More...

Inheritance diagram for statistics:

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Collaboration diagram for statistics:

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List of all members.


Architectures

statistics_arc Architecture
 Determines minimum, maximum and average of a series of input values. More...

Libraries

ieee 
 standard IEEE library

Packages

std_logic_1164 
 std_logic definitions, see file
numeric_std 
 arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file

Generics

SERIES_LENGTH  integer := 4096

Ports

CLK  in std_logic
 Clock.
RES  in std_logic
 Reset.
VAL  in std_logic_vector ( 15 downto 0 )
 Input value.
MNM  out std_logic_vector ( 15 downto 0 )
 Minimum.
MAX  out std_logic_vector ( 15 downto 0 )
 Maximum.
AVG  out std_logic_vector ( 15 downto 0 )
 Average.


Detailed Description

Determines minimum, maximum and average of a series of input values.

This entity determines the minimum & maximum value as well as the average of a series of input values. The series length is specified via a generic that needs to be a power of two.

Definition at line 34 of file statistics.vhd.


Member Data Documentation

AVG out std_logic_vector ( 15 downto 0 ) [Port]

Average.

Definition at line 45 of file statistics.vhd.

CLK in std_logic [Port]

Clock.

Definition at line 40 of file statistics.vhd.

ieee library [Library]

standard IEEE library

Reimplemented in main_components.

Definition at line 24 of file statistics.vhd.

MAX out std_logic_vector ( 15 downto 0 ) [Port]

Maximum.

Definition at line 44 of file statistics.vhd.

MNM out std_logic_vector ( 15 downto 0 ) [Port]

Minimum.

Definition at line 43 of file statistics.vhd.

numeric_std package [Package]

arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file

Definition at line 28 of file statistics.vhd.

RES in std_logic [Port]

Reset.

Definition at line 41 of file statistics.vhd.

std_logic_1164 package [Package]

std_logic definitions, see file

Reimplemented in main_components.

Definition at line 26 of file statistics.vhd.

VAL in std_logic_vector ( 15 downto 0 ) [Port]

Input value.

Definition at line 42 of file statistics.vhd.


The documentation for this class was generated from the following file:

Author: M.Niegl
Generated on Tue Nov 4 01:00:13 2008 for BCM-AAA by doxygen 1.5.7.1-20081012