Architectures | |
statistics_arc | Architecture |
Determines minimum, maximum and average of a series of input values. More... | |
Libraries | |
ieee | |
standard IEEE library | |
Packages | |
std_logic_1164 | |
std_logic definitions, see file | |
numeric_std | |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
Generics | |
SERIES_LENGTH | integer := 4096 |
Ports | |
CLK | in std_logic |
Clock. | |
RES | in std_logic |
Reset. | |
VAL | in std_logic_vector ( 15 downto 0 ) |
Input value. | |
MNM | out std_logic_vector ( 15 downto 0 ) |
Minimum. | |
MAX | out std_logic_vector ( 15 downto 0 ) |
Maximum. | |
AVG | out std_logic_vector ( 15 downto 0 ) |
Average. |
This entity determines the minimum & maximum value as well as the average of a series of input values. The series length is specified via a generic that needs to be a power of two.
Definition at line 34 of file statistics.vhd.
AVG out std_logic_vector ( 15 downto 0 ) [Port] |
CLK in std_logic [Port] |
ieee library [Library] |
standard IEEE library
Reimplemented in main_components.
Definition at line 24 of file statistics.vhd.
MAX out std_logic_vector ( 15 downto 0 ) [Port] |
MNM out std_logic_vector ( 15 downto 0 ) [Port] |
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 28 of file statistics.vhd.
RES in std_logic [Port] |
std_logic_1164 package [Package] |
std_logic definitions, see file
Reimplemented in main_components.
Definition at line 26 of file statistics.vhd.
VAL in std_logic_vector ( 15 downto 0 ) [Port] |