l1a_fifo Entity Reference
FIFO core for L1As. More...
Inheritance diagram for l1a_fifo:
Collaboration diagram for l1a_fifo:
Architectures | |
| l1a_fifo_a | Architecture |
| FIFO core for L1As. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| XilinxCoreLib | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
Ports | |
| clk | in std_logic |
| Clock. | |
| din | in std_logic_vector ( 43 downto 0 ) |
| Data in. | |
| rd_en | in std_logic |
| Read enable. | |
| srst | in std_logic |
| Synchronous reset. | |
| wr_en | in std_logic |
| Write enable. | |
| dout | out std_logic_vector ( 43 downto 0 ) |
| Data out. | |
| empty | out std_logic |
| Empty flag, deasserted after 2 writes!!! | |
| full | out std_logic |
| Full flag. | |
Detailed Description
FIFO core for L1As.
FIFO core for L1As
Stores BCID for accepted bunch as well as corresponding Level-1 ID. Generated with Xilinx FIFO Generator v4.2
Definition at line 73 of file l1a_fifo.vhd.
Member Data Documentation
clk in std_logic [Port] |
din in std_logic_vector ( 43 downto 0 ) [Port] |
dout out std_logic_vector ( 43 downto 0 ) [Port] |
empty out std_logic [Port] |
full out std_logic [Port] |
ieee library [Library] |
rd_en in std_logic [Port] |
srst in std_logic [Port] |
std_logic_1164 package [Package] |
std_logic definitions, see file
Reimplemented in main_components.
Definition at line 64 of file l1a_fifo.vhd.
wr_en in std_logic [Port] |
The documentation for this class was generated from the following file:
