rio_rxtx.rio_rxtx_arc Architecture Reference

DAQ-RocketIO wrapper and support logic. More...

Inheritance diagram for rio_rxtx.rio_rxtx_arc:

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Collaboration diagram for rio_rxtx.rio_rxtx_arc:

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List of all members.

Processes
auto_shift_set1	( mgt0_usr_clk2_i )
	XOR pattern reco.
auto_shift_set2	( mgt1_usr_clk2_i )
	XOR pattern reco.
tx_res	( drp_clk_in_i )
	Extend the TX_SYSTEM_RESET_IN signal using the DRP_CLK.
rx_res	( drp_clk_in_i )
	Extend the RX_SYSTEM_RESET_IN signal using the DRP_CLK.
Components
rio
	RocketIO wrapper.
GT11_INIT_TX	<Entity GT11_INIT_TX>
	Init logic for TX.
GT11_INIT_RX	<Entity GT11_INIT_RX>
	Init logic for RX.
Signals
SHIFT1	integer range 0 to 7 := 0
SHIFT2	integer range 0 to 7 := 0
valid1	std_logic := ' 0 '
valid2	std_logic := ' 0 '
data_out_1	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
data_out_2	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
refclk1_i	std_logic
pulse_clk_p	std_logic
usr_clk2_i	std_logic
mgt0_usr_clk2_i	std_logic
mgt1_usr_clk2_i	std_logic
drp_clk_in_i	std_logic
mgt0_active_i	std_logic
mgt1_active_i	std_logic
mgt0_rxlock_i	std_logic
mgt0_txlock_i	std_logic
mgt1_rxlock_i	std_logic
mgt1_txlock_i	std_logic
mgt0_rxdata_i	std_logic_vector ( 31 downto 0 )
mgt1_rxdata_i	std_logic_vector ( 31 downto 0 )
mgt0_rxdata_iout	std_logic_vector ( 31 downto 0 )
mgt1_rxdata_iout	std_logic_vector ( 31 downto 0 )
mgt0_rx1n_i	std_logic
mgt0_rx1p_i	std_logic
mgt0_tx1n_i	std_logic
mgt0_tx1p_i	std_logic
mgt1_rx1n_i	std_logic
mgt1_rx1p_i	std_logic
mgt1_tx1n_i	std_logic
mgt1_tx1p_i	std_logic
mgt0_rxstatus_i	std_logic_vector ( 5 downto 0 )
mgt1_rxstatus_i	std_logic_vector ( 5 downto 0 )
mgt0_txdata_i	std_logic_vector ( 31 downto 0 )
mgt1_txdata_i	std_logic_vector ( 31 downto 0 )
xor_tx_rx	std_logic_vector ( 31 downto 0 )
xor_tx_rx1	std_logic_vector ( 31 downto 0 )
xor_tx_rx2	std_logic_vector ( 31 downto 0 )
mgt0_rxrecclk1_i	std_logic
mgt0_rxrecclk2_i	std_logic
mgt0_txoutclk1_i	std_logic
mgt0_txoutclk2_i	std_logic
mgt1_rxrecclk1_i	std_logic
mgt1_rxrecclk2_i	std_logic
mgt1_txoutclk1_i	std_logic
mgt1_txoutclk2_i	std_logic
mgt1_txusrclk2_i	std_logic
debounce_tx_system_reset_r	std_logic_vector ( 0 to 3 )
debounce_rx_system_reset_r	std_logic_vector ( 0 to 3 )
rxbuferr_i	std_logic
rxlock_i	std_logic
rx_pmareset_c	std_logic
rx_system_ready_i	std_logic
rx_sync_i	std_logic
rxreset_c	std_logic
rx_system_reset_c	std_logic
rx_system_reset_in_i	std_logic
rx_usrclks_stable_i	std_logic
rx_user_logic_reset_c	std_logic
txbuferr_i	std_logic
tx_pmareset_c	std_logic
tx_post_sync_reset_i	std_logic
txreset_c	std_logic
tx_system_reset_c	std_logic
tx_system_reset_in_i	std_logic
tx_system_ready_i	std_logic
tied_to_ground_i	std_logic
tied_to_ground_vec_i	std_logic_vector ( 63 downto 0 )
tied_to_vcc_i	std_logic
txlock_i	std_logic
tx_sync_i	std_logic
tx_usrclks_stable_i	std_logic
drp_reset_i	std_logic
ch1	std_logic
ch2	std_logic
tgff1	std_logic
tgff2	std_logic
recclklatch0	std_logic
recclklatch1	std_logic
tile0_combusout_a_i	std_logic_vector ( 15 downto 0 )
tile0_combusout_b_i	std_logic_vector ( 15 downto 0 )
Component Instantiations
MGT0_USRCLK2_BUF	BUFR
	buffer clock for support logic
MGT1_USRCLK2_BUF	BUFR
	buffer clock for support logic
gt11_init_tx_i	GT11_INIT_TX <Entity GT11_INIT_TX>
gt11_init_rx_i	GT11_INIT_RX <Entity GT11_INIT_RX>
rio1	rio
	RocketIO 1.
rio2	rio
	RocketIO 2.

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Detailed Description

DAQ-RocketIO wrapper and support logic.

This architecture instantiates the RocketIO primitive wrapper and its support blocks for proper initialization. Furthermore it aligns the RX data and takes care of the needed reset and clocking schemes. As the RocketIOs need a large amount of transitions in the incoming datastream for the RX-PLL to lock, a fixed pattern is sent out with the TX and XORed with the actual data externally. Inside the FPGA it is XORed in parallel after the RocketIOs again with the same pattern for full data reconstruction. This procedure is performed after booting the FPGA with the detector data masked while the procedure is running.

Definition at line 100 of file rio_rxtx.vhd.

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Member Function Documentation

[Process]

auto_shift_set1

( mgt0_usr_clk2_i )

XOR pattern reco.

Definition at line 385 of file rio_rxtx.vhd.

  auto_shift_set1 : process(mgt0_usr_clk2_i)
  begin
    if mgt0_usr_clk2_i'event and mgt0_usr_clk2_i = '1' then
      if (TX_SYSTEM_RESET_IN or RX_SYSTEM_RESET_IN) = '1' then
        valid1     <= '0';
        SHIFT1     <= 0;
        tgff1      <= '0';
        MASK1      <= '0';
        xor_tx_rx1 <= mgt0_txdata_i;
      else
        if (CALIB or CAL1) = '1' then
          if valid1 = '0' then
            if ch1 = '1' then
              if tgff1 = '0' then
                tgff1      <= '1';
                xor_tx_rx1 <= xor_tx_rx1(30 downto 0) & xor_tx_rx1(31);
                --SHIFT1 <= SHIFT1 + 1;
              else
                tgff1 <= '0';
              end if;
            else
              --SHIFT1 <= SHIFT1;
              valid1 <= '1';
              MASK1  <= '1';
            end if;
          end if;
        end if;
      end if;
    end if;
  end process auto_shift_set1;

[Process]

auto_shift_set2

( mgt1_usr_clk2_i )

XOR pattern reco.

Definition at line 417 of file rio_rxtx.vhd.

  auto_shift_set2 : process(mgt1_usr_clk2_i)
  begin
    if mgt1_usr_clk2_i'event and mgt1_usr_clk2_i = '1' then
      if (TX_SYSTEM_RESET_IN or RX_SYSTEM_RESET_IN) = '1' then
        valid2     <= '0';
        SHIFT2     <= 0;
        tgff2      <= '0';
        MASK2      <= '0';
        xor_tx_rx2 <= mgt1_txdata_i;
      else
        if (CALIB or CAL2) = '1' then
          if valid2 = '0' then
            if ch2 = '1' then
              if tgff2 = '0' then
                tgff2      <= '1';
                xor_tx_rx2 <= xor_tx_rx2(30 downto 0) & xor_tx_rx2(31);
                --SHIFT2 <= SHIFT2 + 1;
              else
                tgff2 <= '0';
              end if;
            else
              --SHIFT2 <= SHIFT2;
              valid2 <= '1';
              MASK2  <= '1';
            end if;
          end if;
        end if;
      end if;
    end if;
  end process auto_shift_set2;

[Process]

rx_res

( drp_clk_in_i )

Extend the RX_SYSTEM_RESET_IN signal using the DRP_CLK.

Definition at line 526 of file rio_rxtx.vhd.

  rx_res : process(drp_clk_in_i)
  begin
    if(drp_clk_in_i'event and drp_clk_in_i = '1') then
      debounce_rx_system_reset_r <= rx_system_reset_in_i & debounce_rx_system_reset_r(0 to 2);
    end if;
  end process rx_res;

[Process]

tx_res

( drp_clk_in_i )

Extend the TX_SYSTEM_RESET_IN signal using the DRP_CLK.

Definition at line 513 of file rio_rxtx.vhd.

  tx_res : process(drp_clk_in_i)
  begin
    if(drp_clk_in_i'event and drp_clk_in_i = '1') then
      debounce_tx_system_reset_r <= tx_system_reset_in_i & debounce_tx_system_reset_r(0 to 2);
    end if;
  end process tx_res;

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Member Data Documentation

GT11_INIT_RX [Component]

Init logic for RX.

Definition at line 299 of file rio_rxtx.vhd.

gt11_init_rx_i GT11_INIT_RX [Component Instantiation]

This module is responsible for performing the correct reset and lock procedure as recommended in the user guide

Definition at line 579 of file rio_rxtx.vhd.

GT11_INIT_TX [Component]

Init logic for TX.

Definition at line 278 of file rio_rxtx.vhd.

gt11_init_tx_i GT11_INIT_TX [Component Instantiation]

This module is responsible for performing the correct reset and lock procedure as recommended in the user guide

Definition at line 559 of file rio_rxtx.vhd.

MGT0_USRCLK2_BUF BUFR [Component Instantiation]

buffer clock for support logic

Definition at line 485 of file rio_rxtx.vhd.

MGT1_USRCLK2_BUF BUFR [Component Instantiation]

buffer clock for support logic

Definition at line 494 of file rio_rxtx.vhd.

rio [Component]

RocketIO wrapper.

Definition at line 208 of file rio_rxtx.vhd.

rio1 rio [Component Instantiation]

RocketIO 1.

Definition at line 602 of file rio_rxtx.vhd.

rio2 rio [Component Instantiation]

RocketIO 2.

Definition at line 665 of file rio_rxtx.vhd.

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The documentation for this class was generated from the following file:

• rio_rxtx.vhd