Architectures | |
rtl | Architecture |
calibration logic for SATA RocketIO clocks More... | |
Libraries | |
ieee | |
standard IEEE library | |
work | |
Packages | |
std_logic_1164 | |
std_logic definitions, see file | |
numeric_std | |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
all | |
Generics | |
C_MGT_ID | integer := 0 |
0 = MGTA | 1 = MGTB | |
C_TXPOST_TAP_PD | string := " true " |
Default POST TAP PD. | |
C_RXDIGRX | string := " false " |
Default RXDIGRX. | |
Ports | |
USER_DO | out std_logic_vector ( 16-1 downto 0 ) |
USER_DI | in std_logic_vector ( 16-1 downto 0 ) |
USER_DADDR | in std_logic_vector ( 8-1 downto 0 ) |
USER_DEN | in std_logic |
USER_DWE | in std_logic |
USER_DRDY | out std_logic |
GT_DO | out std_logic_vector ( 16-1 downto 0 ) |
GT_DI | in std_logic_vector ( 16-1 downto 0 ) |
GT_DADDR | out std_logic_vector ( 8-1 downto 0 ) |
GT_DEN | out std_logic |
GT_DWE | out std_logic |
GT_DRDY | in std_logic |
DCLK | in std_logic |
RESET | in std_logic |
ACTIVE | out std_logic |
USER_LOOPBACK | in std_logic_vector ( 1 downto 0 ) |
USER_TXENC8B10BUSE | in std_logic |
USER_TXBYPASS8B10B | in std_logic_vector ( 7 downto 0 ) |
GT_LOOPBACK | out std_logic_vector ( 1 downto 0 ) |
GT_TXENC8B10BUSE | out std_logic |
GT_TXBYPASS8B10B | out std_logic_vector ( 7 downto 0 ) |
TX_SIGNAL_DETECT | in std_logic |
RX_SIGNAL_DETECT | in std_logic |
Attributes | |
use_sync_reset | string |
use_sync_reset | " yes " |
use_sync_set | string |
use_sync_set | " yes " |
use_clock_enable | string |
use_clock_enable | " yes " |
use_dsp48 | string |
use_dsp48 | " no " |
this modules optimizes the PLL performance
Definition at line 85 of file sata_cal_block_v1_4_1.vhd.
C_MGT_ID integer := 0 [Generic] |
C_RXDIGRX string := " false " [Generic] |
C_TXPOST_TAP_PD string := " true " [Generic] |
ieee library [Library] |
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 79 of file sata_cal_block_v1_4_1.vhd.
std_logic_1164 package [Package] |