ddr2_mem_parameters_0 Package Reference
Header file for DDR2 RAM controller. More...
Collaboration diagram for ddr2_mem_parameters_0:
Libraries | |
| ieee | |
| standard IEEE library | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
Constants | |
| data_width | integer := 64 |
| data_strobe_width | integer := 8 |
| data_mask_width | integer := 8 |
| clk_width | integer := 1 |
| fifo | integer := 4 |
| ecc_cntrl_bits | integer := 0 |
| ReadEnable | integer := 3 |
| cs_width | integer := 1 |
| odt_width | integer := 1 |
| cke_width | integer := 1 |
| deep_memory | integer := 1 |
| row_address | integer := 14 |
| column_address | integer := 10 |
| bank_address | integer := 2 |
| memory_width | integer := 8 |
| registered | integer := 1 |
| unbuffered | integer := 0 |
| col_ap_width | integer := 11 |
| DatabitsPerStrobe | integer := 8 |
| DatabitsPerMask | integer := 8 |
| no_of_CS | integer := 1 |
| RESET | integer := 1 |
| data_mask | integer := 1 |
| ecc_enable | integer := 0 |
| ecc_disable | integer := 1 |
| ecc_width | integer := 0 |
| dq_width | integer := 64 |
| dm_width | integer := 8 |
| tb_enable | integer := 0 |
| tb_disable | integer := 1 |
| dcm_enable | integer := 1 |
| dcm_disable | integer := 0 |
| low_frequency | integer := 0 |
| high_frequency | integer := 1 |
| foundation_ise | integer := 1 |
| Data8PerReadEnable | integer := 1 |
| Data4PerReadEnable | integer := 0 |
| burst_length | std_logic_vector ( 2 downto 0 ) := " 011 " |
| burst_type | std_logic := ' 0 ' |
| cas_latency_value | std_logic_vector ( 2 downto 0 ) := " 100 " |
| mode | std_logic := ' 0 ' |
| dll_rst | std_logic := ' 0 ' |
| write_recovery | std_logic_vector ( 2 downto 0 ) := " 010 " |
| pd_mode | std_logic := ' 0 ' |
| load_mode_register | std_logic_vector ( 13 downto 0 ) := " 00010001000011 " |
| output | std_logic := ' 0 ' |
| rdqs_ena | std_logic := ' 0 ' |
| dqs_n_ena | std_logic := ' 0 ' |
| ocd_operation | std_logic_vector ( 2 downto 0 ) := " 000 " |
| odt_enable | std_logic_vector ( 1 downto 0 ) := " 00 " |
| additive_latency_value | std_logic_vector ( 2 downto 0 ) := " 010 " |
| dll_ena | std_logic := ' 0 ' |
| op_drive_strength | std_logic := ' 0 ' |
| ext_load_mode_register | std_logic_vector ( 13 downto 0 ) := " 00000000010000 " |
| chip_address | integer := 1 |
| rcd_count_value | std_logic_vector ( 2 downto 0 ) := " 010 " |
| ras_count_value | std_logic_vector ( 3 downto 0 ) := " 0111 " |
| mrd_count_value | std_logic := ' 1 ' |
| rp_count_value | std_logic_vector ( 2 downto 0 ) := " 010 " |
| rfc_count_value | std_logic_vector ( 5 downto 0 ) := " 001110 " |
| trtp_count_value | std_logic_vector ( 2 downto 0 ) := " 001 " |
| twr_count_value | std_logic_vector ( 2 downto 0 ) := " 011 " |
| twtr_count_value | std_logic_vector ( 2 downto 0 ) := " 001 " |
| max_ref_width | integer := 7 |
| max_ref_cnt | std_logic_vector ( 6 downto 0 ) := " 1011111 " |
| Phy_Mode | std_logic := ' 1 ' |
| cs_h0 | std_logic_vector ( 3 downto 0 ) := " 0000 " |
| cs_h1 | std_logic_vector ( 3 downto 0 ) := " 0001 " |
| cs_h2 | std_logic_vector ( 3 downto 0 ) := " 0010 " |
| cs_h3 | std_logic_vector ( 3 downto 0 ) := " 0011 " |
| cs_h5 | std_logic_vector ( 3 downto 0 ) := " 0101 " |
| cs_h6 | std_logic_vector ( 3 downto 0 ) := " 0110 " |
| cs_h7 | std_logic_vector ( 3 downto 0 ) := " 0111 " |
| cs_hA | std_logic_vector ( 3 downto 0 ) := " 1010 " |
| cs_hB | std_logic_vector ( 3 downto 0 ) := " 1011 " |
| cs_hD | std_logic_vector ( 3 downto 0 ) := " 1101 " |
| cs_hE | std_logic_vector ( 3 downto 0 ) := " 1110 " |
| cs_hF | std_logic_vector ( 3 downto 0 ) := " 1111 " |
| cs_D100 | std_logic_vector ( 7 downto 0 ) := X " 64 " |
| cs_D1000 | std_logic_vector ( 11 downto 0 ) := X " 3E8 " |
| add_const1 | std_logic_vector ( 15 downto 0 ) := X " 0100 " |
| add_const2 | std_logic_vector ( 15 downto 0 ) := X " 0380 " |
| add_const3 | std_logic_vector ( 15 downto 0 ) := X " 0000 " |
| add_const4 | std_logic_vector ( 15 downto 0 ) := X " FBFF " |
| add_const5 | std_logic_vector ( 15 downto 0 ) := X " FFFF " |
Types | |
| STATE_MACHINE1 | ( rise_idle , rise_first_data , rise_second_data , rise_comp_over ) |
| FSM1 enum, pattern compare. | |
| STATE_MACHINE2 | ( fall_idle , fall_first_data , fall_second_data , fall_comp_over ) |
| FSM2 enum, pattern compare. | |
Detailed Description
Header file for DDR2 RAM controller.
According to the user inputs the parameters are defined here. These parameters are used for the generic memory interface code. Various parameters are address widths, data widths, timing parameters according to the frequency selected by the user and some internal parameters also. counter values in the controller in tCK units:
write latency (WL) = Read Latency (RL) - 1 = AL + CL -1
Read Latency (RL ) = AL + CL
Definition at line 56 of file ddr2_mem_parameters_0.vhd.
Member Data Documentation
ieee library [Library] |
STATE_MACHINE1 ( rise_idle , rise_first_data , rise_second_data , rise_comp_over ) [Type] |
STATE_MACHINE2 ( fall_idle , fall_first_data , fall_second_data , fall_comp_over ) [Type] |
std_logic_1164 package [Package] |
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 45 of file ddr2_mem_parameters_0.vhd.
The documentation for this class was generated from the following file:
