ddr2_mem_rd_data_0 Entity Reference
Read datapath. More...
Inheritance diagram for ddr2_mem_rd_data_0:
Collaboration diagram for ddr2_mem_rd_data_0:
Architectures | |
| arc_rd_data | Architecture |
| Read datapath. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| work | |
| unisim | |
| Library with Xilinx primitives. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
| numeric_std | |
| arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
| ddr2_mem_parameters_0 | Package <ddr2_mem_parameters_0> |
| vcomponents | |
| Header with Xilinx primitives. | |
Ports | |
| CLK | in std_logic |
| clock | |
| RESET | in std_logic |
| reset | |
| CTRL_RDEN | in std_logic |
| read enable | |
| READ_DATA_RISE | in std_logic_vector ( data_width-1 downto 0 ) |
| read data rising edge | |
| READ_DATA_FALL | in std_logic_vector ( data_width-1 downto 0 ) |
| read data falling edge | |
| READ_DATA_FIFO_RISE | out std_logic_vector ( data_width-1 downto 0 ) |
| read data rising edge | |
| READ_DATA_FIFO_FALL | out std_logic_vector ( data_width-1 downto 0 ) |
| read data falling edge | |
| READ_DATA_VALID | out std_logic |
| data valid | |
| COMP_DONE | out std_logic |
| done flag | |
Detailed Description
Read datapath.The delay between the read data with respect to the command issued is calculted in terms of no. of clocks. This data is then stored into the FIFOs and then read back and given as the ouput for comparison.
Definition at line 63 of file ddr2_mem_rd_data_0.vhd.
Member Data Documentation
CLK in std_logic [Port] |
COMP_DONE out std_logic [Port] |
CTRL_RDEN in std_logic [Port] |
ieee library [Library] |
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 48 of file ddr2_mem_rd_data_0.vhd.
READ_DATA_FALL in std_logic_vector ( data_width-1 downto 0 ) [Port] |
READ_DATA_FIFO_FALL out std_logic_vector ( data_width-1 downto 0 ) [Port] |
READ_DATA_FIFO_RISE out std_logic_vector ( data_width-1 downto 0 ) [Port] |
READ_DATA_RISE in std_logic_vector ( data_width-1 downto 0 ) [Port] |
READ_DATA_VALID out std_logic [Port] |
RESET in std_logic [Port] |
std_logic_1164 package [Package] |
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 46 of file ddr2_mem_rd_data_0.vhd.
unisim library [Library] |
vcomponents package [Package] |
The documentation for this class was generated from the following file:
