ethbuf Entity Reference
Wrapper for DPRAM Buffer core. More...
Inheritance diagram for ethbuf:
Collaboration diagram for ethbuf:
Architectures | |
| ethbuf_arc | Architecture |
| DPBRAM instantiation. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| XilinxCoreLib | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
Ports | |
| addra | in std_logic_vector ( 8 downto 0 ) |
| read address | |
| addrb | in std_logic_vector ( 4 downto 0 ) |
| write address | |
| clka | in std_logic |
| read clock | |
| clkb | in std_logic |
| write clock | |
| dinb | in std_logic_vector ( 127 downto 0 ) |
| write data | |
| douta | out std_logic_vector ( 7 downto 0 ) |
| read data | |
| ena | in std_logic |
| read enable | |
| enb | in std_logic |
| enable write port | |
| web | in std_logic |
| write enable | |
Detailed Description
Wrapper for DPRAM Buffer core.Definition at line 69 of file ethbuf.vhd.
Member Data Documentation
addra in std_logic_vector ( 8 downto 0 ) [Port] |
addrb in std_logic_vector ( 4 downto 0 ) [Port] |
clka in std_logic [Port] |
clkb in std_logic [Port] |
dinb in std_logic_vector ( 127 downto 0 ) [Port] |
douta out std_logic_vector ( 7 downto 0 ) [Port] |
ena in std_logic [Port] |
enb in std_logic [Port] |
ieee library [Library] |
std_logic_1164 package [Package] |
web in std_logic [Port] |
The documentation for this class was generated from the following file:
