ddr2_mem_tap_logic_0.arc_tap_logic Architecture Reference
Data tap module. More...
Inheritance diagram for ddr2_mem_tap_logic_0.arc_tap_logic:
Collaboration diagram for ddr2_mem_tap_logic_0.arc_tap_logic:
Processes | |
| PROCESS_162 | ( CLK ) |
| For controller to stop dummy reads. | |
Components | |
| ddr2_mem_tap_ctrl | <Entity ddr2_mem_tap_ctrl> |
| Tap controller. | |
| ddr2_mem_data_tap_inc | <Entity ddr2_mem_data_tap_inc> |
| Tap unit. | |
Signals | |
| data_tap_select | std_logic_vector ( ReadEnable-1 downto 0 ) |
| dqs_tap_sel_done | std_logic_vector ( ReadEnable-1 downto 0 ) |
| valid_tap_count | std_logic_vector ( ReadEnable-1 downto 0 ) |
| data_tap_count0 | std_logic_vector ( 5 downto 0 ) |
| data_tap_count1 | std_logic_vector ( 5 downto 0 ) |
| data_tap_count2 | std_logic_vector ( 5 downto 0 ) |
| data_tap_inc_done | std_logic |
| tap_sel_done | std_logic |
Component Instantiations | |
| tap_ctrl_0 | ddr2_mem_tap_ctrl <Entity ddr2_mem_tap_ctrl> |
| tap_ctrl instances for DDR_DQS strobes | |
| tap_ctrl_1 | ddr2_mem_tap_ctrl <Entity ddr2_mem_tap_ctrl> |
| tap_ctrl instances for DDR_DQS strobes | |
| tap_ctrl_2 | ddr2_mem_tap_ctrl <Entity ddr2_mem_tap_ctrl> |
| tap_ctrl instances for DDR_DQS strobes | |
| data_tap_inc_0 | ddr2_mem_data_tap_inc <Entity ddr2_mem_data_tap_inc> |
| instance of data_tap_inc for each dqs and associated tap_ctrl | |
| data_tap_inc_1 | ddr2_mem_data_tap_inc <Entity ddr2_mem_data_tap_inc> |
| instance of data_tap_inc for each dqs and associated tap_ctrl | |
| data_tap_inc_2 | ddr2_mem_data_tap_inc <Entity ddr2_mem_data_tap_inc> |
| instance of data_tap_inc for each dqs and associated tap_ctrl | |
Detailed Description
Data tap module.This module instantiates the tap_cntrl and the data_tap_inc modules. Used for calibration of the memory data with the FPGA clock.
Definition at line 83 of file ddr2_mem_tap_logic_0.vhd.
Member Function Documentation
| PROCESS_162 | ( CLK ) |
For controller to stop dummy reads.
Definition at line 131 of file ddr2_mem_tap_logic_0.vhd.
00131 process(CLK) 00132 begin 00133 if CLK'event and CLK = '1' then 00134 if (RESET0 = '1') then 00135 data_tap_inc_done <= '0'; 00136 tap_sel_done <= '0'; 00137 else 00138 data_tap_inc_done <= data_tap_select(0) and data_tap_select(1) and data_tap_select(2); 00139 tap_sel_done <= data_tap_inc_done; 00140 end if; 00141 end if; 00142 end process;
Member Data Documentation
data_tap_inc_0 ddr2_mem_data_tap_inc [Component Instantiation] |
instance of data_tap_inc for each dqs and associated tap_ctrl
Definition at line 199 of file ddr2_mem_tap_logic_0.vhd.
data_tap_inc_1 ddr2_mem_data_tap_inc [Component Instantiation] |
instance of data_tap_inc for each dqs and associated tap_ctrl
Definition at line 213 of file ddr2_mem_tap_logic_0.vhd.
data_tap_inc_2 ddr2_mem_data_tap_inc [Component Instantiation] |
instance of data_tap_inc for each dqs and associated tap_ctrl
Definition at line 227 of file ddr2_mem_tap_logic_0.vhd.
ddr2_mem_data_tap_inc [Component] |
ddr2_mem_tap_ctrl [Component] |
tap_ctrl_0 ddr2_mem_tap_ctrl [Component Instantiation] |
tap_ctrl_1 ddr2_mem_tap_ctrl [Component Instantiation] |
tap_ctrl_2 ddr2_mem_tap_ctrl [Component Instantiation] |
The documentation for this class was generated from the following file:
