ddr2_mem_data_path_iobs_0 Entity Reference

Datapath IOBs. More...

Inheritance diagram for ddr2_mem_data_path_iobs_0:

Inheritance graph
[legend]
Collaboration diagram for ddr2_mem_data_path_iobs_0:

Collaboration graph
[legend]

List of all members.


Architectures

arc_data_path_iobs Architecture
 Datapath IOBs. More...

Libraries

ieee 
 standard IEEE library
work 
unisim 
 Library with Xilinx primitives.

Packages

std_logic_1164 
 std_logic definitions, see file
std_logic_unsigned 
 unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
numeric_std 
 arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
ddr2_mem_parameters_0  Package <ddr2_mem_parameters_0>
vcomponents 
 Header with Xilinx primitives.

Ports

CLK  in std_logic
CLK90  in std_logic
CAL_CLK  in std_logic
RESET0  in std_logic
RESET90  in std_logic
dqs_idelay_inc  in std_logic_vector ( readenable-1 downto 0 )
dqs_idelay_ce  in std_logic_vector ( readenable-1 downto 0 )
dqs_idelay_rst  in std_logic_vector ( readenable-1 downto 0 )
dqs_rst  in std_logic
dqs_en  in std_logic
dqs_delayed  out std_logic_vector ( data_strobe_width-1 downto 0 )
data_idelay_inc  in std_logic_vector ( readenable-1 downto 0 )
data_idelay_ce  in std_logic_vector ( readenable-1 downto 0 )
data_idelay_rst  in std_logic_vector ( readenable-1 downto 0 )
wr_data_rise  in std_logic_vector ( data_width-1 downto 0 )
wr_data_fall  in std_logic_vector ( data_width-1 downto 0 )
mask_data_rise  in std_logic_vector ( data_mask_width-1 downto 0 )
mask_data_fall  in std_logic_vector ( data_mask_width-1 downto 0 )
wr_en  in std_logic
DDR_DQ  inout std_logic_vector ( data_width-1 downto 0 )
DDR_DQS  inout std_logic_vector ( data_strobe_width-1 downto 0 )
DDR_DQS_L  inout std_logic_vector ( data_strobe_width-1 downto 0 )
DDR_DM  out std_logic_vector ( data_mask_width-1 downto 0 )
rd_data_rise  out std_logic_vector ( data_width-1 downto 0 )
rd_data_fall  out std_logic_vector ( data_width-1 downto 0 )


Detailed Description

Datapath IOBs.

This module instantiates data, data strobe and the data mask iobs.

Definition at line 58 of file ddr2_mem_data_path_iobs_0.vhd.


Member Data Documentation

ieee library [Library]

standard IEEE library

Definition at line 42 of file ddr2_mem_data_path_iobs_0.vhd.

numeric_std package [Package]

arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file

Definition at line 48 of file ddr2_mem_data_path_iobs_0.vhd.

std_logic_1164 package [Package]

std_logic definitions, see file

Definition at line 44 of file ddr2_mem_data_path_iobs_0.vhd.

std_logic_unsigned package [Package]

unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file

Definition at line 46 of file ddr2_mem_data_path_iobs_0.vhd.

unisim library [Library]

Library with Xilinx primitives.

Definition at line 52 of file ddr2_mem_data_path_iobs_0.vhd.

vcomponents package [Package]

Header with Xilinx primitives.

Definition at line 54 of file ddr2_mem_data_path_iobs_0.vhd.


The documentation for this class was generated from the following file:

Author: M.Niegl
Generated on Tue Nov 4 00:49:56 2008 for BCM-AAA by doxygen 1.5.7.1-20081012