ddr2_mem_data_path_0 Entity Reference
Calibration structure for data. More...
Inheritance diagram for ddr2_mem_data_path_0:
Collaboration diagram for ddr2_mem_data_path_0:
Architectures | |
| arc_data_path | Architecture |
| Calibration structure for data. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| work | |
| unisim | |
| Library with Xilinx primitives. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
| numeric_std | |
| arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
| ddr2_mem_parameters_0 | Package <ddr2_mem_parameters_0> |
| vcomponents | |
| Header with Xilinx primitives. | |
Ports | |
| CLK | in std_logic |
| CLK90 | in std_logic |
| CAL_CLK | in std_logic |
| RESET0 | in std_logic |
| RESET90 | in std_logic |
| RESET_CAL_CLK | in std_logic |
| CTRL_DUMMYREAD_START | in std_logic |
| idelay_ctrl_rdy | in std_logic |
| WDF_DATA | in std_logic_vector ( dq_width *2-1 downto 0 ) |
| MASK_DATA | in std_logic_vector ( dm_width *2-1 downto 0 ) |
| CTRL_WREN | in std_logic |
| CTRL_DQS_RST | in std_logic |
| CTRL_DQS_EN | in std_logic |
| dqs_delayed | in std_logic_vector ( data_strobe_width-1 downto 0 ) |
| CTRL_DUMMY_WR_SEL | in std_logic |
| dummy_write_flag | in std_logic |
| wr_data_rise | out std_logic_vector ( data_width-1 downto 0 ) |
| wr_data_fall | out std_logic_vector ( data_width-1 downto 0 ) |
| mask_data_rise | out std_logic_vector ( data_mask_width-1 downto 0 ) |
| mask_data_fall | out std_logic_vector ( data_mask_width-1 downto 0 ) |
| wr_en | out std_logic |
| dqs_rst | out std_logic |
| dqs_en | out std_logic |
| dqs_idelay_inc | out std_logic_vector ( readenable-1 downto 0 ) |
| dqs_idelay_ce | out std_logic_vector ( readenable-1 downto 0 ) |
| dqs_idelay_rst | out std_logic_vector ( readenable-1 downto 0 ) |
| data_idelay_inc | out std_logic_vector ( readenable-1 downto 0 ) |
| data_idelay_ce | out std_logic_vector ( readenable-1 downto 0 ) |
| data_idelay_rst | out std_logic_vector ( readenable-1 downto 0 ) |
| SEL_DONE | out std_logic |
Detailed Description
Calibration structure for data.This module instantiates the tap logic and the data write modules. Gives the rise and the fall data and the calibration information for the IDELAY elements.
Definition at line 63 of file ddr2_mem_data_path_0.vhd.
Member Data Documentation
ieee library [Library] |
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 49 of file ddr2_mem_data_path_0.vhd.
std_logic_1164 package [Package] |
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 47 of file ddr2_mem_data_path_0.vhd.
unisim library [Library] |
vcomponents package [Package] |
The documentation for this class was generated from the following file:
