ddr2_mem_idelay_ctrl Entity Reference
IDELAYCTRL primitive. More...
Inheritance diagram for ddr2_mem_idelay_ctrl:
Collaboration diagram for ddr2_mem_idelay_ctrl:
Architectures | |
| arc_idelay_ctrl | Architecture |
| IDELAYCTRL instantiation More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| unisim | |
| Library with Xilinx primitives. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
| numeric_std | |
| arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
| vcomponents | |
| Header with Xilinx primitives. | |
Ports | |
| CLK200 | in std_logic |
| 200 MHz clock | |
| RESET | in std_logic |
| Reset. | |
| RDY_STATUS | out std_logic |
| Status Flag. | |
Detailed Description
IDELAYCTRL primitive.This module instantaites the IDELAYCTRL primitive of the Virtex4 device which continously calibrates the IDELAY elements in the region in case of varying operating conditions. It takes a 200MHz clock as an input.
Definition at line 43 of file ddr2_mem_idelay_ctrl.vhd.
Member Data Documentation
CLK200 in std_logic [Port] |
ieee library [Library] |
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 30 of file ddr2_mem_idelay_ctrl.vhd.
RDY_STATUS out std_logic [Port] |
RESET in std_logic [Port] |
std_logic_1164 package [Package] |
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 28 of file ddr2_mem_idelay_ctrl.vhd.
unisim library [Library] |
vcomponents package [Package] |
The documentation for this class was generated from the following file:
