cnt_ddr_rd Entity Reference
Counter for accesses to DDR. More...
Inheritance diagram for cnt_ddr_rd:
Collaboration diagram for cnt_ddr_rd:
Architectures | |
| cnt_ddr_rd_arc | Architecture |
| Counter for accesses to DDR. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_arith | |
| arithmetic operations on std_logic datatypes, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
Ports | |
| RESET | in std_logic |
| Reset. | |
| CLK | in std_logic |
| Clock. | |
| EN | in std_logic |
| Enable. | |
| DONE | out std_logic |
| Overflow flag. | |
Attributes | |
| use_dsp48 | string |
| XST specific attribute for DSP cores. | |
| use_dsp48 | " yes " |
| force XST to infer DSP48 cores | |
Detailed Description
Counter for accesses to DDR.Definition at line 32 of file cnt_ddr_rd.vhd.
Member Data Documentation
CLK in std_logic [Port] |
DONE out std_logic [Port] |
EN in std_logic [Port] |
ieee library [Library] |
standard IEEE library
Reimplemented in main_components.
Definition at line 23 of file cnt_ddr_rd.vhd.
RESET in std_logic [Port] |
std_logic_1164 package [Package] |
std_logic definitions, see file
Reimplemented in main_components.
Definition at line 25 of file cnt_ddr_rd.vhd.
std_logic_arith package [Package] |
arithmetic operations on std_logic datatypes, see file
Definition at line 27 of file cnt_ddr_rd.vhd.
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 29 of file cnt_ddr_rd.vhd.
use_dsp48 " yes " [Attribute] |
use_dsp48 string [Attribute] |
The documentation for this class was generated from the following file:
