GT11_INIT_RX Entity Reference

Initializer for RocketIO RX. More...

Inheritance diagram for GT11_INIT_RX:

Inheritance graph
[legend]
Collaboration diagram for GT11_INIT_RX:

Collaboration graph
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List of all members.


Architectures

rtl Architecture
 Initialization logic for RocketIO RX. More...

Libraries

ieee 
 standard IEEE library
unisim 
 Library with Xilinx primitives.

Packages

std_logic_1164 
 std_logic definitions, see file
numeric_std 
 arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
vcomponents 
 Header with Xilinx primitives.

Generics

C_SIMULATION  integer := 0
 Set to 1 for simulation.

Ports

CLK  in std_logic
 Clock.
START_INIT  in std_logic
 Start of init flag.
LOCK  in std_logic
 PLL lock flag.
USRCLK_STABLE  in std_logic
 Clock stable flag.
PCS_ERROR  in std_logic
 PCS error flag.
PMA_RESET  out std_logic
 PMA reset.
SYNC  out std_logic
 Syncronization flag.
PCS_RESET  out std_logic
 PCS reset.
READY  out std_logic
 Done flag.


Detailed Description

Initializer for RocketIO RX.

Definition at line 57 of file gt11_init_rx.vhd.


Member Data Documentation

C_SIMULATION integer := 0 [Generic]

Set to 1 for simulation.

Definition at line 59 of file gt11_init_rx.vhd.

CLK in std_logic [Port]

Clock.

Definition at line 63 of file gt11_init_rx.vhd.

ieee library [Library]

standard IEEE library

Definition at line 43 of file gt11_init_rx.vhd.

LOCK in std_logic [Port]

PLL lock flag.

Definition at line 65 of file gt11_init_rx.vhd.

numeric_std package [Package]

arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file

Definition at line 47 of file gt11_init_rx.vhd.

PCS_ERROR in std_logic [Port]

PCS error flag.

Definition at line 67 of file gt11_init_rx.vhd.

PCS_RESET out std_logic [Port]

PCS reset.

Definition at line 70 of file gt11_init_rx.vhd.

PMA_RESET out std_logic [Port]

PMA reset.

Definition at line 68 of file gt11_init_rx.vhd.

READY out std_logic [Port]

Done flag.

Definition at line 71 of file gt11_init_rx.vhd.

START_INIT in std_logic [Port]

Start of init flag.

Definition at line 64 of file gt11_init_rx.vhd.

std_logic_1164 package [Package]

std_logic definitions, see file

Definition at line 45 of file gt11_init_rx.vhd.

SYNC out std_logic [Port]

Syncronization flag.

Definition at line 69 of file gt11_init_rx.vhd.

unisim library [Library]

Library with Xilinx primitives.

Definition at line 50 of file gt11_init_rx.vhd.

USRCLK_STABLE in std_logic [Port]

Clock stable flag.

Definition at line 66 of file gt11_init_rx.vhd.

vcomponents package [Package]

Header with Xilinx primitives.

Definition at line 52 of file gt11_init_rx.vhd.


The documentation for this class was generated from the following file:

Author: M.Niegl
Generated on Tue Nov 4 00:51:28 2008 for BCM-AAA by doxygen 1.5.7.1-20081012