Architectures | |
rtl | Architecture |
Initialization logic for RocketIO RX. More... | |
Libraries | |
ieee | |
standard IEEE library | |
unisim | |
Library with Xilinx primitives. | |
Packages | |
std_logic_1164 | |
std_logic definitions, see file | |
numeric_std | |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
vcomponents | |
Header with Xilinx primitives. | |
Generics | |
C_SIMULATION | integer := 0 |
Set to 1 for simulation. | |
Ports | |
CLK | in std_logic |
Clock. | |
START_INIT | in std_logic |
Start of init flag. | |
LOCK | in std_logic |
PLL lock flag. | |
USRCLK_STABLE | in std_logic |
Clock stable flag. | |
PCS_ERROR | in std_logic |
PCS error flag. | |
PMA_RESET | out std_logic |
PMA reset. | |
SYNC | out std_logic |
Syncronization flag. | |
PCS_RESET | out std_logic |
PCS reset. | |
READY | out std_logic |
Done flag. |
Definition at line 57 of file gt11_init_rx.vhd.
C_SIMULATION integer := 0 [Generic] |
CLK in std_logic [Port] |
ieee library [Library] |
LOCK in std_logic [Port] |
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 47 of file gt11_init_rx.vhd.
PCS_ERROR in std_logic [Port] |
PCS_RESET out std_logic [Port] |
PMA_RESET out std_logic [Port] |
READY out std_logic [Port] |
START_INIT in std_logic [Port] |
std_logic_1164 package [Package] |
SYNC out std_logic [Port] |
unisim library [Library] |
USRCLK_STABLE in std_logic [Port] |
vcomponents package [Package] |