sata Entity Reference

SATA wrapper. More...

Inheritance diagram for sata:

Collaboration diagram for sata:

List of all members.

Architectures

sata_arc Architecture

SATA wrapper. More...

Libraries

ieee

standard IEEE library

unisim

Library with Xilinx primitives.

Packages

std_logic_1164

std_logic definitions, see file

std_logic_arith

arithmetic operations on std_logic datatypes, see file

std_logic_unsigned

unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file

vcomponents

Header with Xilinx primitives.

Generics

C_SIMULATION integer := 0

Set to 1 for simulation.

Ports

CLK_RIO_IN in std_logic

RIOs reference clock.

CLK_DRP_IN in std_logic

50MHz system clock for PLL correction (used) and DRP (not used), used also for reset clocking since it is slover than TXOUTCLK1/2 = 75 MHz

CLK_DATA_IN in std_logic

clock for data Retrieval

USRCLK_STABLE_IN in std_logic

stable then '1' --signaling stable inputs of input clocks

TX_A_SYSTEM_RESET_IN in std_logic

reset signal for both TX

TX_B_SYSTEM_RESET_IN in std_logic

reset signal for both TX

RXP_SATA_IN in std_logic_vector ( 1 downto 0 )

package pins

RXN_SATA_IN in std_logic_vector ( 1 downto 0 )

package pins

TXP_SATA_OUT out std_logic_vector ( 1 downto 0 )

package pins

TXN_SATA_OUT out std_logic_vector ( 1 downto 0 )

package pins

MGTA_TXLOCK_OUT out std_logic

PLL lock state.

MGTA_RXLOCK_OUT out std_logic

PLL lock state.

MGTB_TXLOCK_OUT out std_logic

PLL lock state.

MGTB_RXLOCK_OUT out std_logic

PLL lock state.

TX_A_READY out std_logic

transmitrers ready

RX_A_READY out std_logic

receivers ready

TX_B_READY out std_logic

transmitrers ready

RX_B_READY out std_logic

receivers ready

A_DATA_IN in std_logic_vector ( 31 downto 0 )

data to be send

B_DATA_IN in std_logic_vector ( 31 downto 0 )

data to be send

A_DATA_CONTROL_IN in std_logic_vector ( 3 downto 0 )

'1' bits encodes coresponding byte as comma character

B_DATA_CONTROL_IN in std_logic_vector ( 3 downto 0 )

'1' bits encodes coresponding byte as comma character

A_DATA_READY_IN in std_logic

'1' if data is to be sent '0' if there is no data

B_DATA_READY_IN in std_logic

'1' if data is to be sent '0' if there is no data

A_EOP_IN in std_logic

initiate the end of package sequence --must be only one CLK_DATA_IN cycle long

B_EOP_IN in std_logic

initiate the end of package sequence --must be only one CLK_DATA_IN cycle long

A_DATA_OUT out std_logic_vector ( 31 downto 0 )

data received

B_DATA_OUT out std_logic_vector ( 31 downto 0 )

data received

A_DATA_READY_OUT out std_logic

'1' if received data is avalible, '0' if there is no data

B_DATA_READY_OUT out std_logic

'1' if received data is avalible, '0' if there is no data

A_DATA_CONTROL_OUT out std_logic_vector ( 3 downto 0 )

'1' bit coresponds to byte as comma character

B_DATA_CONTROL_OUT out std_logic_vector ( 3 downto 0 )

'1' bit coresponds to byte as comma character

A_EOP_OUT out std_logic

signals, that end of package has been received

B_EOP_OUT out std_logic

signals, that end of package has been received

A_PACKAGE_OK_OUT out std_logic

four CLK_DATA_IN cycles lather than EOP_OUT this signal indicates whether previous packet was received correctly

B_PACKAGE_OK_OUT out std_logic

four CLK_DATA_IN cycles lather than EOP_OUT this signal indicates whether previous packet was received correctly

A_DATA_ERROR_OUT out std_logic

'1' if error ocoured, '0' if ok

B_DATA_ERROR_OUT out std_logic

'1' if error ocoured, '0' if ok

SCOPE_OUT out std_logic_vector ( 191 downto 0 )

chipscope

Detailed Description

SATA wrapper.

Definition at line 37 of file sata.vhd.

Member Data Documentation

A_DATA_CONTROL_IN in std_logic_vector ( 3 downto 0 ) [Port]

'1' bits encodes coresponding byte as comma character

Definition at line 68 of file sata.vhd.

A_DATA_CONTROL_OUT out std_logic_vector ( 3 downto 0 ) [Port]

'1' bit coresponds to byte as comma character

Definition at line 78 of file sata.vhd.

A_DATA_ERROR_OUT out std_logic [Port]

'1' if error ocoured, '0' if ok

Definition at line 84 of file sata.vhd.

A_DATA_IN in std_logic_vector ( 31 downto 0 ) [Port]

data to be send

Definition at line 66 of file sata.vhd.

A_DATA_OUT out std_logic_vector ( 31 downto 0 ) [Port]

data received

Definition at line 74 of file sata.vhd.

A_DATA_READY_IN in std_logic [Port]

'1' if data is to be sent '0' if there is no data

Definition at line 70 of file sata.vhd.

A_DATA_READY_OUT out std_logic [Port]

'1' if received data is avalible, '0' if there is no data

Definition at line 76 of file sata.vhd.

A_EOP_IN in std_logic [Port]

initiate the end of package sequence --must be only one CLK_DATA_IN cycle long

Definition at line 72 of file sata.vhd.

A_EOP_OUT out std_logic [Port]

signals, that end of package has been received

Definition at line 80 of file sata.vhd.

A_PACKAGE_OK_OUT out std_logic [Port]

four CLK_DATA_IN cycles lather than EOP_OUT this signal indicates whether previous packet was received correctly

Definition at line 82 of file sata.vhd.

B_DATA_CONTROL_IN in std_logic_vector ( 3 downto 0 ) [Port]

'1' bits encodes coresponding byte as comma character

Definition at line 69 of file sata.vhd.

B_DATA_CONTROL_OUT out std_logic_vector ( 3 downto 0 ) [Port]

'1' bit coresponds to byte as comma character

Definition at line 79 of file sata.vhd.

B_DATA_ERROR_OUT out std_logic [Port]

'1' if error ocoured, '0' if ok

Definition at line 85 of file sata.vhd.

B_DATA_IN in std_logic_vector ( 31 downto 0 ) [Port]

data to be send

Definition at line 67 of file sata.vhd.

B_DATA_OUT out std_logic_vector ( 31 downto 0 ) [Port]

data received

Definition at line 75 of file sata.vhd.

B_DATA_READY_IN in std_logic [Port]

'1' if data is to be sent '0' if there is no data

Definition at line 71 of file sata.vhd.

B_DATA_READY_OUT out std_logic [Port]

'1' if received data is avalible, '0' if there is no data

Definition at line 77 of file sata.vhd.

B_EOP_IN in std_logic [Port]

initiate the end of package sequence --must be only one CLK_DATA_IN cycle long

Definition at line 73 of file sata.vhd.

B_EOP_OUT out std_logic [Port]

signals, that end of package has been received

Definition at line 81 of file sata.vhd.

B_PACKAGE_OK_OUT out std_logic [Port]

four CLK_DATA_IN cycles lather than EOP_OUT this signal indicates whether previous packet was received correctly

Definition at line 83 of file sata.vhd.

C_SIMULATION integer := 0 [Generic]

Set to 1 for simulation.

Definition at line 39 of file sata.vhd.

CLK_DATA_IN in std_logic [Port]

clock for data Retrieval

Definition at line 46 of file sata.vhd.

CLK_DRP_IN in std_logic [Port]

50MHz system clock for PLL correction (used) and DRP (not used), used also for reset clocking since it is slover than TXOUTCLK1/2 = 75 MHz

Definition at line 45 of file sata.vhd.

CLK_RIO_IN in std_logic [Port]

RIOs reference clock.

Definition at line 44 of file sata.vhd.

ieee library [Library]

standard IEEE library

Reimplemented in main_components.

Definition at line 24 of file sata.vhd.

MGTA_RXLOCK_OUT out std_logic [Port]

PLL lock state.

Definition at line 58 of file sata.vhd.

MGTA_TXLOCK_OUT out std_logic [Port]

PLL lock state.

Definition at line 57 of file sata.vhd.

MGTB_RXLOCK_OUT out std_logic [Port]

PLL lock state.

Definition at line 60 of file sata.vhd.

MGTB_TXLOCK_OUT out std_logic [Port]

PLL lock state.

Definition at line 59 of file sata.vhd.

RX_A_READY out std_logic [Port]

receivers ready

Definition at line 62 of file sata.vhd.

RX_B_READY out std_logic [Port]

receivers ready

Definition at line 64 of file sata.vhd.

RXN_SATA_IN in std_logic_vector ( 1 downto 0 ) [Port]

package pins

Definition at line 53 of file sata.vhd.

RXP_SATA_IN in std_logic_vector ( 1 downto 0 ) [Port]

package pins

Definition at line 52 of file sata.vhd.

SCOPE_OUT out std_logic_vector ( 191 downto 0 ) [Port]

chipscope

Definition at line 87 of file sata.vhd.

std_logic_1164 package [Package]

std_logic definitions, see file

Reimplemented in main_components.

Definition at line 26 of file sata.vhd.

std_logic_arith package [Package]

arithmetic operations on std_logic datatypes, see file

Definition at line 28 of file sata.vhd.

std_logic_unsigned package [Package]

unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file

Definition at line 30 of file sata.vhd.

TX_A_READY out std_logic [Port]

transmitrers ready

Definition at line 61 of file sata.vhd.

TX_A_SYSTEM_RESET_IN in std_logic [Port]

reset signal for both TX

Definition at line 49 of file sata.vhd.

TX_B_READY out std_logic [Port]

transmitrers ready

Definition at line 63 of file sata.vhd.

TX_B_SYSTEM_RESET_IN in std_logic [Port]

reset signal for both TX

Definition at line 50 of file sata.vhd.

TXN_SATA_OUT out std_logic_vector ( 1 downto 0 ) [Port]

package pins

Definition at line 55 of file sata.vhd.

TXP_SATA_OUT out std_logic_vector ( 1 downto 0 ) [Port]

package pins

Definition at line 54 of file sata.vhd.

unisim library [Library]

Library with Xilinx primitives.

Definition at line 32 of file sata.vhd.

USRCLK_STABLE_IN in std_logic [Port]

stable then '1' --signaling stable inputs of input clocks

Definition at line 47 of file sata.vhd.

vcomponents package [Package]

Header with Xilinx primitives.

Definition at line 34 of file sata.vhd.

The documentation for this class was generated from the following file:

sata.vhd


Architectures
sata_arc	Architecture
	SATA wrapper. More...
Libraries
ieee
	standard IEEE library
unisim
	Library with Xilinx primitives.
Packages
std_logic_1164
	std_logic definitions, see file
std_logic_arith
	arithmetic operations on std_logic datatypes, see file
std_logic_unsigned
	unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
vcomponents
	Header with Xilinx primitives.
Generics
C_SIMULATION	integer := 0
	Set to 1 for simulation.
Ports
CLK_RIO_IN	in std_logic
	RIOs reference clock.
CLK_DRP_IN	in std_logic
	50MHz system clock for PLL correction (used) and DRP (not used), used also for reset clocking since it is slover than TXOUTCLK1/2 = 75 MHz
CLK_DATA_IN	in std_logic
	clock for data Retrieval
USRCLK_STABLE_IN	in std_logic
	stable then '1' --signaling stable inputs of input clocks
TX_A_SYSTEM_RESET_IN	in std_logic
	reset signal for both TX
TX_B_SYSTEM_RESET_IN	in std_logic
	reset signal for both TX
RXP_SATA_IN	in std_logic_vector ( 1 downto 0 )
	package pins
RXN_SATA_IN	in std_logic_vector ( 1 downto 0 )
	package pins
TXP_SATA_OUT	out std_logic_vector ( 1 downto 0 )
	package pins
TXN_SATA_OUT	out std_logic_vector ( 1 downto 0 )
	package pins
MGTA_TXLOCK_OUT	out std_logic
	PLL lock state.
MGTA_RXLOCK_OUT	out std_logic
	PLL lock state.
MGTB_TXLOCK_OUT	out std_logic
	PLL lock state.
MGTB_RXLOCK_OUT	out std_logic
	PLL lock state.
TX_A_READY	out std_logic
	transmitrers ready
RX_A_READY	out std_logic
	receivers ready
TX_B_READY	out std_logic
	transmitrers ready
RX_B_READY	out std_logic
	receivers ready
A_DATA_IN	in std_logic_vector ( 31 downto 0 )
	data to be send
B_DATA_IN	in std_logic_vector ( 31 downto 0 )
	data to be send
A_DATA_CONTROL_IN	in std_logic_vector ( 3 downto 0 )
	'1' bits encodes coresponding byte as comma character
B_DATA_CONTROL_IN	in std_logic_vector ( 3 downto 0 )
	'1' bits encodes coresponding byte as comma character
A_DATA_READY_IN	in std_logic
	'1' if data is to be sent '0' if there is no data
B_DATA_READY_IN	in std_logic
	'1' if data is to be sent '0' if there is no data
A_EOP_IN	in std_logic
	initiate the end of package sequence --must be only one CLK_DATA_IN cycle long
B_EOP_IN	in std_logic
	initiate the end of package sequence --must be only one CLK_DATA_IN cycle long
A_DATA_OUT	out std_logic_vector ( 31 downto 0 )
	data received
B_DATA_OUT	out std_logic_vector ( 31 downto 0 )
	data received
A_DATA_READY_OUT	out std_logic
	'1' if received data is avalible, '0' if there is no data
B_DATA_READY_OUT	out std_logic
	'1' if received data is avalible, '0' if there is no data
A_DATA_CONTROL_OUT	out std_logic_vector ( 3 downto 0 )
	'1' bit coresponds to byte as comma character
B_DATA_CONTROL_OUT	out std_logic_vector ( 3 downto 0 )
	'1' bit coresponds to byte as comma character
A_EOP_OUT	out std_logic
	signals, that end of package has been received
B_EOP_OUT	out std_logic
	signals, that end of package has been received
A_PACKAGE_OK_OUT	out std_logic
	four CLK_DATA_IN cycles lather than EOP_OUT this signal indicates whether previous packet was received correctly
B_PACKAGE_OK_OUT	out std_logic
	four CLK_DATA_IN cycles lather than EOP_OUT this signal indicates whether previous packet was received correctly
A_DATA_ERROR_OUT	out std_logic
	'1' if error ocoured, '0' if ok
B_DATA_ERROR_OUT	out std_logic
	'1' if error ocoured, '0' if ok
SCOPE_OUT	out std_logic_vector ( 191 downto 0 )
	chipscope