ddr2_mem_tap_ctrl Entity Reference
Tap control logic. More...
Inheritance diagram for ddr2_mem_tap_ctrl:
Collaboration diagram for ddr2_mem_tap_ctrl:
Architectures | |
| arch | Architecture |
| Tap control logic. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| unisim | |
| Library with Xilinx primitives. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_unsigned | |
| unsigned functions & operators for std_logic_vector type, see file | |
| vcomponents | |
| Header with Xilinx primitives. | |
Ports | |
| CAL_CLK | in std_logic |
| RESET | in std_logic |
| RDY_STATUS | in std_logic |
| DQS | in std_logic |
| CTRL_DUMMYREAD_START | in std_logic |
| DLYINC | out std_logic |
| DLYCE | out std_logic |
| DLYRST | out std_logic |
| SEL_DONE | out std_logic |
| VALID_DATA_TAP_COUNT | out std_logic |
| DATA_TAP_COUNT | out std_logic_vector ( 5 downto 0 ) |
Detailed Description
Tap control logic.The tap control logic which claculates the relation between the FPGA clock and the dqs from memory. It delays the dqs so as to detect the edges of the dqs and then calculates the mid point so that the data can be registered properly.
Definition at line 57 of file ddr2_mem_tap_ctrl.vhd.
Member Data Documentation
ieee library [Library] |
std_logic_1164 package [Package] |
std_logic_unsigned package [Package] |
unsigned functions & operators for std_logic_vector type, see file
Definition at line 46 of file ddr2_mem_tap_ctrl.vhd.
unisim library [Library] |
vcomponents package [Package] |
The documentation for this class was generated from the following file:
