Architectures | |
arc_v4_dm_iob | Architecture |
DDR2 data mask IOBs. More... | |
Libraries | |
ieee | |
standard IEEE library | |
unisim | |
Library with Xilinx primitives. | |
Packages | |
std_logic_1164 | |
std_logic definitions, see file | |
std_logic_unsigned | |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
numeric_std | |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
vcomponents | |
Header with Xilinx primitives. | |
Ports | |
CLK90 | in std_logic |
clock | |
MASK_DATA_RISE | in std_logic |
rising edge data mask | |
MASK_DATA_FALL | in std_logic |
falling edge data mask | |
DDR_DM | out std_logic |
DDR data mask. |
Definition at line 38 of file ddr2_mem_v4_dm_iob.vhd.
CLK90 in std_logic [Port] |
DDR_DM out std_logic [Port] |
ieee library [Library] |
MASK_DATA_FALL in std_logic [Port] |
MASK_DATA_RISE in std_logic [Port] |
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 30 of file ddr2_mem_v4_dm_iob.vhd.
std_logic_1164 package [Package] |
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 28 of file ddr2_mem_v4_dm_iob.vhd.
unisim library [Library] |
vcomponents package [Package] |