ddr2_mem_v4_dm_iob Entity Reference

This module places the data mask signals into the IOBs. More...

Inheritance diagram for ddr2_mem_v4_dm_iob:

Inheritance graph
[legend]
Collaboration diagram for ddr2_mem_v4_dm_iob:

Collaboration graph
[legend]

List of all members.


Architectures

arc_v4_dm_iob Architecture
 DDR2 data mask IOBs. More...

Libraries

ieee 
 standard IEEE library
unisim 
 Library with Xilinx primitives.

Packages

std_logic_1164 
 std_logic definitions, see file
std_logic_unsigned 
 unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
numeric_std 
 arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
vcomponents 
 Header with Xilinx primitives.

Ports

CLK90  in std_logic
 clock
MASK_DATA_RISE  in std_logic
 rising edge data mask
MASK_DATA_FALL  in std_logic
 falling edge data mask
DDR_DM  out std_logic
 DDR data mask.


Detailed Description

This module places the data mask signals into the IOBs.

Definition at line 38 of file ddr2_mem_v4_dm_iob.vhd.


Member Data Documentation

CLK90 in std_logic [Port]

clock

Definition at line 40 of file ddr2_mem_v4_dm_iob.vhd.

DDR_DM out std_logic [Port]

DDR data mask.

Definition at line 43 of file ddr2_mem_v4_dm_iob.vhd.

ieee library [Library]

standard IEEE library

Definition at line 24 of file ddr2_mem_v4_dm_iob.vhd.

MASK_DATA_FALL in std_logic [Port]

falling edge data mask

Definition at line 42 of file ddr2_mem_v4_dm_iob.vhd.

MASK_DATA_RISE in std_logic [Port]

rising edge data mask

Definition at line 41 of file ddr2_mem_v4_dm_iob.vhd.

numeric_std package [Package]

arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file

Definition at line 30 of file ddr2_mem_v4_dm_iob.vhd.

std_logic_1164 package [Package]

std_logic definitions, see file

Definition at line 26 of file ddr2_mem_v4_dm_iob.vhd.

std_logic_unsigned package [Package]

unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file

Definition at line 28 of file ddr2_mem_v4_dm_iob.vhd.

unisim library [Library]

Library with Xilinx primitives.

Definition at line 33 of file ddr2_mem_v4_dm_iob.vhd.

vcomponents package [Package]

Header with Xilinx primitives.

Definition at line 35 of file ddr2_mem_v4_dm_iob.vhd.


The documentation for this class was generated from the following file:

Author: M.Niegl
Generated on Tue Nov 4 00:50:52 2008 for BCM-AAA by doxygen 1.5.7.1-20081012