sata_GT11_INIT_TX.rtl Architecture Reference

RIO-TX initializer. More...

Inheritance diagram for sata_GT11_INIT_TX.rtl:

[legend]

Collaboration diagram for sata_GT11_INIT_TX.rtl:

[legend]

List of all members.

Functions
string	ExtendString ( string_in: in string , string_len: in integer )
	extend a string
Processes
PROCESS_374	( CLK , START_INIT )
	Synchronize Reset.
PROCESS_375	( CLK )
	Synchronize LOCK.
PROCESS_376	( CLK )
	Synchronize PCS_ERROR and generate a pulse when PCS_ERROR is high.
PROCESS_377	( CLK )
	Counter for holding PMA reset for an amount of C_DELAY_PMA_RESET.
PROCESS_378	( CLK )
PROCESS_379	( CLK )
	Counter for holding SYNC for an amount of C_DELAY_SYNC.
PROCESS_380	( CLK )
	Counter for holding PCS reset for an amount of C_DELAY_PCS_RESET.
PROCESS_381	( CLK )
	Counter for waiting C_DELAY_WAIT_PCS after de-assertion of PCS reset.
PROCESS_382	( CLK )
	Counter for PCS error.
PROCESS_383	( CLK )
	Counter for the READY signal.
PROCESS_384	( CLK )
	GT11 Initialization FSM.
PROCESS_385	( reset_r(0) , pma_reset_done_i , init_fsm_wait_lock_check , lock_r , sync_done_i , pcs_reset_done_i , wait_pcs_done_i , pcs_error_r1 , pcs_error_count_done_i , wait_ready_done_i )
Components
FDE
	component FDE
SRL16E
	component SRL16
FDRE
	component FDRE
Constants
C_DELAY_PMA_RESET	unsigned ( 2 downto 0 ) := " 011 "
C_DELAY_SYNC	unsigned ( 7 downto 0 ) := " 01000000 "
C_DELAY_PCS_RESET	unsigned ( 2 downto 0 ) := " 011 "
C_DELAY_LOCK	unsigned ( 4 downto 0 ) := " 10000 "
C_DELAY_WAIT_PCS	unsigned ( 3 downto 0 ) := " 0101 "
C_DELAY_WAIT_READY	unsigned ( 7 downto 0 ) := " 01000000 "
C_PCS_ERROR_COUNT	unsigned ( 4 downto 0 ) := " 10000 "
C_RESET	unsigned ( 7 downto 0 ) := " 00000001 "
	GT11 Initialization FSM.
C_PMA_RESET	unsigned ( 7 downto 0 ) := " 00000010 "
	GT11 Initialization FSM.
C_WAIT_LOCK	unsigned ( 7 downto 0 ) := " 00000100 "
	GT11 Initialization FSM.
C_SYNC	unsigned ( 7 downto 0 ) := " 00001000 "
	GT11 Initialization FSM.
C_PCS_RESET	unsigned ( 7 downto 0 ) := " 00010000 "
	GT11 Initialization FSM.
C_WAIT_PCS	unsigned ( 7 downto 0 ) := " 00100000 "
	GT11 Initialization FSM.
C_ALMOST_READY	unsigned ( 7 downto 0 ) := " 01000000 "
	GT11 Initialization FSM.
C_READY	unsigned ( 7 downto 0 ) := " 10000000 "
	GT11 Initialization FSM.
Signals
reset_r	unsigned ( 1 downto 0 )
lock_r	std_logic
lock_r2	std_logic
pcs_error_r1	std_logic
pcs_error_r2	std_logic
pma_reset_count_r	unsigned ( 2 downto 0 )
sync_count_r	unsigned ( 7 downto 0 )
pcs_reset_count_r	unsigned ( 2 downto 0 )
wait_pcs_count_r	unsigned ( 3 downto 0 )
pcs_error_count_r	unsigned ( 4 downto 0 )
wait_ready_count_r	unsigned ( 7 downto 0 )
init_state_r	unsigned ( 7 downto 0 )
init_next_state_r	unsigned ( 7 downto 0 )
init_fsm_name	unsigned ( 40 *7 downto 0 )
init_fsm_wait_lock_check	std_logic
pma_reset_done_i	std_logic
lock2sync_ready_i	std_logic
sync_done_i	std_logic
pcs_reset_done_i	std_logic
wait_pcs_done_i	std_logic
pcs_error_count_done_i	std_logic
wait_ready_done_i	std_logic
tied_to_ground_i	std_logic
tied_to_vcc_i	std_logic
lock_pulse_i	std_logic
shift_register_0_q_i	std_logic
shift_register_0_d_i	std_logic
shift_register_1_q_i	std_logic
shift_register_1_d_i	std_logic
shift_register_2_q_i	std_logic
shift_register_2_d_i	std_logic
shift_register_3_q_i	std_logic
shift_register_3_d_i	std_logic
stage_1_enable_i	std_logic
stage_2_enable_i	std_logic
stage_3_enable_i	std_logic
shift_register_1_enable_i	std_logic
shift_register_2_enable_i	std_logic
shift_register_3_enable_i	std_logic
not_lock_i	std_logic
Component Instantiations
shift_register_0	SRL16E
	SRL16 Stage Zero - First stage of shifting.
flop_stage_0	FDE
	extra FF, last stage
shift_register_1	SRL16E
	SRL16 Stage One - Second stage of shifting.
flop_stage_1	FDE
	extra FF, last stage
shift_register_2	SRL16E
	SRL16 Stage Two - Third stage of shifting.
flop_stage_2	FDE
	extra FF, last stage
shift_register_3	SRL16E
	SRL16 Stage Three - Fourth stage of shifting.
flop_stage_3	FDRE
	extra FF, last stage

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Detailed Description

RIO-TX initializer.

this entity produces signal sequences for initializing rio tx

Definition at line 79 of file sata_gt11_init_tx.vhd.

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Member Function Documentation

[Function]

string ExtendString		( string_in in string ,
		string_len in integer )

extend a string

Definition at line 208 of file sata_gt11_init_tx.vhd.

  function ExtendString (string_in  : string;
                         string_len : integer) 
    return string is
    variable string_out : string(1 to string_len) := (others => ' ');
  begin
    if string_in'length > string_len then
      string_out := string_in(1 to string_len);
    else
      string_out(1 to string_in'length) := string_in;
    end if;
    return string_out;
  end ExtendString;

[Process]

PROCESS_374		( CLK ,
		START_INIT )

Synchronize Reset.

Definition at line 231 of file sata_gt11_init_tx.vhd.

  process (CLK, START_INIT)
  begin
    if (START_INIT = '1') then
      reset_r <= "11";
    elsif (rising_edge(CLK)) then
      reset_r <= '0' & reset_r(1);
    end if;
  end process;

[Process]

PROCESS_375

( CLK )

Synchronize LOCK.

Definition at line 241 of file sata_gt11_init_tx.vhd.

  process(CLK)
  begin
    if(CLK'event and CLK = '1') then
      if (reset_r(0) = '1') then
        lock_r <= '0';
      else
        lock_r <= LOCK;
      end if;
    end if;
  end process;

[Process]

PROCESS_376

( CLK )

Synchronize PCS_ERROR and generate a pulse when PCS_ERROR is high.

Definition at line 253 of file sata_gt11_init_tx.vhd.

  process(CLK)
  begin
    if(CLK'event and CLK = '1') then
      if(reset_r(0) = '1') then
        pcs_error_r1 <= '0';
      else
        pcs_error_r1 <= PCS_ERROR;
      end if;
    end if;
  end process;

[Process]

PROCESS_377

( CLK )

Counter for holding PMA reset for an amount of C_DELAY_PMA_RESET.

Definition at line 273 of file sata_gt11_init_tx.vhd.

  process(CLK)
  begin
    if(CLK'event and CLK = '1') then
      if(init_state_r /= C_PMA_RESET) then
        pma_reset_count_r <= C_DELAY_PMA_RESET;
      else
        pma_reset_count_r <= pma_reset_count_r - 1;
      end if;
    end if;
  end process;

[Process]

PROCESS_378

( CLK )

Counter for the wait time between assertion of TXLOCK and assertion to TXSYNC cycles. There is a requirement of 12,000 TXUSRCLK2 cycles between these two points. Please refer to the reset section of the User Guide for more information. This is built with SRL16s. In this module, we assume 1 USRCLK2 = 1 USRCLK (please adjust the address of the fourth SRL16 stage as neccessary). The whole four stages give 12,288 cycles of delay (16 * 16 * 16 * 3); note that the last stage has an extra FF at the end. Create a pulse from TXLOCK to initialize SRL16's. Need to register the LOCK signal from the GT11 twice since the LOCK is based on REFCLK

Definition at line 304 of file sata_gt11_init_tx.vhd.

    process(CLK)
    begin
      if(CLK'event and CLK = '1') then
        if (reset_r(0) = '1') then
          lock_r2 <= '0';
        else
          lock_r2 <= lock_r;
        end if;
      end if;
    end process;

[Process]

PROCESS_379

( CLK )

Counter for holding SYNC for an amount of C_DELAY_SYNC.

Definition at line 439 of file sata_gt11_init_tx.vhd.

  process(CLK)
  begin
    if(CLK'event and CLK = '1') then
      if(init_state_r /= C_SYNC) then
        sync_count_r <= C_DELAY_SYNC;
      else
        sync_count_r <= sync_count_r - 1;
      end if;
    end if;
  end process;

[Process]

PROCESS_380

( CLK )

Counter for holding PCS reset for an amount of C_DELAY_PCS_RESET.

Definition at line 453 of file sata_gt11_init_tx.vhd.

  process(CLK)
  begin
    if(CLK'event and CLK = '1') then
      if(init_state_r /= C_PCS_RESET) then
        pcs_reset_count_r <= C_DELAY_PCS_RESET;
      else
        pcs_reset_count_r <= pcs_reset_count_r - 1;
      end if;
    end if;
  end process;

[Process]

PROCESS_381

( CLK )

Counter for waiting C_DELAY_WAIT_PCS after de-assertion of PCS reset.

Definition at line 467 of file sata_gt11_init_tx.vhd.

  process(CLK)
  begin
    if(CLK'event and CLK = '1') then
      if(init_state_r /= C_WAIT_PCS) then
        wait_pcs_count_r <= C_DELAY_WAIT_PCS;
      else
        wait_pcs_count_r <= wait_pcs_count_r - 1;
      end if;
    end if;
  end process;

[Process]

PROCESS_382

( CLK )

Counter for PCS error.

Definition at line 481 of file sata_gt11_init_tx.vhd.

  process(CLK)
  begin
    if(CLK'event and CLK = '1') then
      if(init_state_r = C_PMA_RESET) then
        pcs_error_count_r <= C_PCS_ERROR_COUNT;
      elsif (((init_state_r = C_ALMOST_READY) or (init_state_r = C_READY)) and (pcs_error_r1 and lock_r) = '1') then
        pcs_error_count_r <= pcs_error_count_r - 1;
      end if;
    end if;
  end process;

[Process]

PROCESS_383

( CLK )

Counter for the READY signal.

Definition at line 495 of file sata_gt11_init_tx.vhd.

  process(CLK)
  begin
    if(CLK'event and CLK = '1') then
      if((init_state_r /= C_ALMOST_READY) or (pcs_error_r1 = '1')) then
        wait_ready_count_r <= C_DELAY_WAIT_READY;
      elsif(pcs_error_r1 = '0') then
        wait_ready_count_r <= wait_ready_count_r - 1;
      end if;
    end if;
  end process;

[Process]

PROCESS_384

( CLK )

GT11 Initialization FSM.

Definition at line 509 of file sata_gt11_init_tx.vhd.

  process (CLK)
  begin
    if (rising_edge(CLK)) then
      if (reset_r(0) = '1') then
        init_state_r <= C_RESET;
      else
        init_state_r <= init_next_state_r;
      end if;
    end if;
  end process;

[Process]

PROCESS_385		( reset_r(0) ,
		pma_reset_done_i ,
		init_fsm_wait_lock_check ,
		lock_r ,
		sync_done_i ,
		pcs_reset_done_i ,
		wait_pcs_done_i ,
		pcs_error_r1 ,
		pcs_error_count_done_i ,
		wait_ready_done_i )

GT11 Initialization FSM - This FSM is used to initialize the GT11 block asserting the PMA and PCS reset in sequence. It also takes into account of any error that may happen during initialization. The block uses USRCLK as reference for the delay. DO NOT use the output of the GT11 clocks for this reset module, as the output clocks may change when reset is applied to the GT11. Use a system clock, and make sure that the wait time for each state equals the specified number of USRCLK cycles.

The following steps are applied: 1. C_RESET: Upon system reset of this block, PMA reset will be asserted 2. C_PMA_RESET: PMA reset is held for 3 USRCLK cycles 3. C_WAIT_LOCK: Wait for LOCK. After LOCK is asserted, wait for 12,000 USRCLK2 cycles and wait for the USRCLK of the GT11s to be stable before going to the next state to assert the PCS reset. If LOCK gets de-asserted, we reset the counter and wait for LOCK again. 4. C_SYNC: Assert SYNG for 64 SYNC cycles. If LOCK gets de-asserted, we go back to Step 3. 5. C_PCS_RESET: Assert PCS reset for 3 USRCLK cycles. If LOCK gets de-asserted, we go back to Step 3. 6. C_WAIT_PCS: After de-assertion of PCS reset, wait 5 USRCLK cycles. If LOCK gets de-asserted, we go back to Step 3. 7. C_ALMOST_READY: Go to the Almost Ready state. If LOCK gets de-asserted, we go back to Step 3. If there is a PCS error (i.e. buffer error) detected while LOCK is high, we go back to Step 4. If we cycle PCS reset for an N number of C_PCS_ERROR_COUNT, we go back to Step 1 to do a PMA reset. 8. C_READY: Go to the Ready state. We reach this state after waiting 64 USRCLK cycles without any PCS errors. We assert the READY signal to denote that this block finishes initializing the GT11. If there is a PCS error during this state, we go back to Step 4. If LOCK is lost, we go back to Step 3.

Definition at line 553 of file sata_gt11_init_tx.vhd.

  process (reset_r(0), pma_reset_done_i, init_fsm_wait_lock_check, lock_r,
           sync_done_i, pcs_reset_done_i, wait_pcs_done_i, pcs_error_r1,
           pcs_error_count_done_i, wait_ready_done_i)
    variable init_fsm_name : string(1 to 25);
  begin
    case init_state_r is
      
      when C_RESET =>
        
        if (reset_r(0) = '1') then
          init_next_state_r <= C_RESET;
        else
          init_next_state_r <= C_PMA_RESET;
        end if;
        init_fsm_name := ExtendString("C_RESET", 25);

      when C_PMA_RESET =>

        if (pma_reset_done_i = '1') then
          init_next_state_r <= C_WAIT_LOCK;
        else
          init_next_state_r <= C_PMA_RESET;
        end if;
        init_fsm_name := ExtendString("C_PMA_RESET", 25);

      when C_WAIT_LOCK =>

        if(init_fsm_wait_lock_check = '1') then
          init_next_state_r <= C_SYNC;
        else
          init_next_state_r <= C_WAIT_LOCK;
        end if;
        init_fsm_name := ExtendString("C_WAIT_LOCK", 25);

      when C_SYNC =>
        if (lock_r = '1') then
          if (sync_done_i = '1') then
            init_next_state_r <= C_PCS_RESET;
          else
            init_next_state_r <= C_SYNC;
          end if;
        else
          init_next_state_r <= C_WAIT_LOCK;
        end if;
        init_fsm_name := ExtendString("C_SYNC", 25);

      when C_PCS_RESET =>
        if (lock_r = '1') then
          if (pcs_reset_done_i = '1') then
            init_next_state_r <= C_WAIT_PCS;
          else
            init_next_state_r <= C_PCS_RESET;
          end if;
        else
          init_next_state_r <= C_WAIT_LOCK;
        end if;
        init_fsm_name := ExtendString("C_PCS_RESET", 25);

      when C_WAIT_PCS =>
        if (lock_r = '1') then
          if (wait_pcs_done_i = '1') then
            init_next_state_r <= C_ALMOST_READY;
          else
            init_next_state_r <= C_WAIT_PCS;
          end if;
        else
          init_next_state_r <= C_WAIT_LOCK;
        end if;
        init_fsm_name := ExtendString("C_WAIT_PCS", 25);

      when C_ALMOST_READY =>
        if (lock_r = '0') then
          init_next_state_r <= C_WAIT_LOCK;
        elsif ((pcs_error_r1 = '1') and (pcs_error_count_done_i = '0')) then
          init_next_state_r <= C_SYNC;
        elsif ((pcs_error_r1 = '1') and (pcs_error_count_done_i = '1')) then
          init_next_state_r <= C_PMA_RESET;
        elsif (wait_ready_done_i = '1') then
          init_next_state_r <= C_READY;
        else
          init_next_state_r <= C_ALMOST_READY;
        end if;
        init_fsm_name := ExtendString("C_ALMOST_READY", 25);

      when C_READY =>
        if ((lock_r = '1') and (pcs_error_r1 = '0')) then
          init_next_state_r <= C_READY;
        elsif ((lock_r = '1') and (pcs_error_r1 = '1')) then
          init_next_state_r <= C_PCS_RESET;
        else
          init_next_state_r <= C_WAIT_LOCK;
        end if;
        init_fsm_name := ExtendString("C_READY", 25);

      when others =>
        init_next_state_r <= C_RESET;
        init_fsm_name     := ExtendString("C_RESET", 25);

    end case;
  end process;

---

Member Data Documentation

C_ALMOST_READY unsigned ( 7 downto 0 ) := " 01000000 " [Constant]

GT11 Initialization FSM.

Definition at line 107 of file sata_gt11_init_tx.vhd.

C_PCS_RESET unsigned ( 7 downto 0 ) := " 00010000 " [Constant]

GT11 Initialization FSM.

Definition at line 103 of file sata_gt11_init_tx.vhd.

C_PMA_RESET unsigned ( 7 downto 0 ) := " 00000010 " [Constant]

GT11 Initialization FSM.

Definition at line 97 of file sata_gt11_init_tx.vhd.

C_READY unsigned ( 7 downto 0 ) := " 10000000 " [Constant]

GT11 Initialization FSM.

Definition at line 109 of file sata_gt11_init_tx.vhd.

C_RESET unsigned ( 7 downto 0 ) := " 00000001 " [Constant]

GT11 Initialization FSM.

Definition at line 95 of file sata_gt11_init_tx.vhd.

C_SYNC unsigned ( 7 downto 0 ) := " 00001000 " [Constant]

GT11 Initialization FSM.

Definition at line 101 of file sata_gt11_init_tx.vhd.

C_WAIT_LOCK unsigned ( 7 downto 0 ) := " 00000100 " [Constant]

GT11 Initialization FSM.

Definition at line 99 of file sata_gt11_init_tx.vhd.

C_WAIT_PCS unsigned ( 7 downto 0 ) := " 00100000 " [Constant]

GT11 Initialization FSM.

Definition at line 105 of file sata_gt11_init_tx.vhd.

FDE [Component]

component FDE

Definition at line 156 of file sata_gt11_init_tx.vhd.

FDRE [Component]

component FDRE

Definition at line 190 of file sata_gt11_init_tx.vhd.

flop_stage_0 FDE [Component Instantiation]

extra FF, last stage

Definition at line 334 of file sata_gt11_init_tx.vhd.

flop_stage_1 FDE [Component Instantiation]

extra FF, last stage

Definition at line 362 of file sata_gt11_init_tx.vhd.

flop_stage_2 FDE [Component Instantiation]

extra FF, last stage

Definition at line 393 of file sata_gt11_init_tx.vhd.

flop_stage_3 FDRE [Component Instantiation]

extra FF, last stage

Definition at line 427 of file sata_gt11_init_tx.vhd.

shift_register_0 SRL16E [Component Instantiation]

SRL16 Stage Zero - First stage of shifting.

Definition at line 320 of file sata_gt11_init_tx.vhd.

shift_register_1 SRL16E [Component Instantiation]

SRL16 Stage One - Second stage of shifting.

Definition at line 348 of file sata_gt11_init_tx.vhd.

shift_register_2 SRL16E [Component Instantiation]

SRL16 Stage Two - Third stage of shifting.

Definition at line 379 of file sata_gt11_init_tx.vhd.

shift_register_3 SRL16E [Component Instantiation]

SRL16 Stage Three - Fourth stage of shifting.

Definition at line 411 of file sata_gt11_init_tx.vhd.

SRL16E [Component]

component SRL16

Definition at line 171 of file sata_gt11_init_tx.vhd.

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The documentation for this class was generated from the following file:

• sata_gt11_init_tx.vhd