sata.sata_arc Architecture Reference
SATA wrapper. More...
Inheritance diagram for sata.sata_arc:
Collaboration diagram for sata.sata_arc:
Processes | |
| PROCESS_327 | ( clk2_usr_i ) |
| PROCESS_328 | ( clk2_usr_not_i ) |
| PROCESS_329 | ( clk2_usr_not_i ) |
| PROCESS_330 | ( mgtA_rxrecclk1_i ) |
| PROCESS_331 | ( mgtB_rxrecclk1_i ) |
| PROCESS_332 | ( mgtA_rxrecclk1_i ) |
| PROCESS_333 | ( mgtB_rxrecclk1_i ) |
Components | |
| ROCKETIO_SATA | <Entity ROCKETIO_SATA> |
| SATA RocketIO wrapper. | |
| sata_gt11_init_tx | |
| sata_gt11_init_rx | |
Signals | |
| tied_to_ground_i | std_logic := ' 0 ' |
| tied_to_ground_vec_i | std_logic_vector ( 63 downto 0 ) |
| tied_to_vcc_i | std_logic := ' 1 ' |
| tied_to_vcc_vec_i | std_logic_vector ( 63 downto 0 ) |
| clk2_usr_i | std_logic |
| clk2_usr_not_i | std_logic |
| clk_drp_in_i | std_logic := ' 0 ' |
| tx_usrclks_stable_i | std_logic |
| rx_usrclks_stable_i | std_logic |
| mgtB_rxrecclk1_i | std_logic |
| mgtB_rxrecclk1_ii | std_logic |
| mgtA_rxrecclk1_i | std_logic |
| mgtA_rxrecclk1_ii | std_logic |
| mgtB_rxrecclk2_i | std_logic |
| mgtA_rxrecclk2_i | std_logic |
| mgtB_txoutclk1_i | std_logic |
| mgtA_txoutclk1_i | std_logic |
| mgtB_txoutclk2_i | std_logic |
| mgtA_txoutclk2_i | std_logic |
| mgt_data_recovered_clk_i | std_logic |
| clk_half_sata | std_logic |
| mgtB_txlock_i | std_logic |
| mgtB_rxlock_i | std_logic |
| mgtA_txlock_i | std_logic |
| mgtA_rxlock_i | std_logic |
| tx_A_system_ready_i | std_logic |
| rx_A_system_ready_i | std_logic |
| tx_B_system_ready_i | std_logic |
| rx_B_system_ready_i | std_logic |
| tx_A_system_reset_in_i | std_logic |
| tx_B_system_reset_in_i | std_logic |
| drpA_reset_i | std_logic |
| drpB_reset_i | std_logic |
| txA_sync_i | std_logic |
| txB_sync_i | std_logic |
| rxA_sync_i | std_logic |
| rxB_sync_i | std_logic |
| txA_pmareset_c | std_logic |
| txB_pmareset_c | std_logic |
| rxA_pmareset_c | std_logic |
| rxB_pmareset_c | std_logic |
| txA_reset_c | std_logic |
| txB_reset_c | std_logic |
| rxA_reset_c | std_logic |
| rxB_reset_c | std_logic |
| mgtB_calibration_active | std_logic |
| mgtA_calibration_active | std_logic |
| mgtB_rxstatus_i | std_logic_vector ( 5 downto 0 ) |
| mgtA_rxstatus_i | std_logic_vector ( 5 downto 0 ) |
| mgtA_OOBsigdet_i | std_logic |
| mgtA_OOBsigsen_i | std_logic |
| mgtB_OOBsigdet_i | std_logic |
| mgtB_OOBsigsen_i | std_logic |
| mgt_tx_inhibit_i | std_logic |
| mgtA_txbypass8b10b_i | std_logic_vector ( 3 downto 0 ) := " 0000 " |
| mgtB_txbypass8b10b_i | std_logic_vector ( 3 downto 0 ) := " 0000 " |
| tile0_combusout_a_i | std_logic_vector ( 15 downto 0 ) |
| tile0_combusout_b_i | std_logic_vector ( 15 downto 0 ) |
| mgtA_rxrealign_i | std_logic |
| mgtA_enmcommaalign_i | std_logic |
| mgtA_enpcommaalign_i | std_logic |
| mgtA_rxcommadet_i | std_logic |
| mgtB_rxrealign_i | std_logic |
| mgtB_enmcommaalign_i | std_logic |
| mgtB_enpcommaalign_i | std_logic |
| mgtB_rxcommadet_i | std_logic |
| align_char_c | std_logic_vector ( 31 downto 0 ) |
| align_control_bits_c | std_logic_vector ( 3 downto 0 ) |
| idle_char_c | std_logic_vector ( 31 downto 0 ) |
| idle_control_bits_c | std_logic_vector ( 3 downto 0 ) |
| mgtA_txcharisk_i | std_logic_vector ( 3 downto 0 ) |
| mgtB_txcharisk_i | std_logic_vector ( 3 downto 0 ) |
| mgtA_rxcharisk_i | std_logic_vector ( 3 downto 0 ) |
| mgtB_rxcharisk_i | std_logic_vector ( 3 downto 0 ) |
| mgtA_rxchariscomma_i | std_logic_vector ( 3 downto 0 ) |
| mgtB_rxchariscomma_i | std_logic_vector ( 3 downto 0 ) |
| encommaalign_A_i | std_logic := ' 0 ' |
| encommaalign_B_i | std_logic := ' 0 ' |
| mgtA_align_detected_i | std_logic := ' 0 ' |
| mgtB_align_detected_i | std_logic := ' 0 ' |
| mgtA_idle_detected_i | std_logic := ' 0 ' |
| mgtB_idle_detected_i | std_logic := ' 0 ' |
| mgtA_tx_data_i | std_logic_vector ( 31 downto 0 ) |
| mgtB_tx_data_i | std_logic_vector ( 31 downto 0 ) |
| mgtA_rx_data_i | std_logic_vector ( 31 downto 0 ) |
| mgtB_rx_data_i | std_logic_vector ( 31 downto 0 ) |
| mgtA_tx_crc_value_i | std_logic_vector ( 31 downto 0 ) |
| mgtB_tx_crc_value_i | std_logic_vector ( 31 downto 0 ) |
| mgtA_data_output_i | std_logic_vector ( 31 downto 0 ) |
| mgtB_data_output_i | std_logic_vector ( 31 downto 0 ) |
| mgtA_txkerr_i | std_logic_vector ( 3 downto 0 ) |
| mgtB_txkerr_i | std_logic_vector ( 3 downto 0 ) |
| mgtA_txrundisp_i | std_logic_vector ( 3 downto 0 ) |
| mgtB_txrundisp_i | std_logic_vector ( 3 downto 0 ) |
| mgtA_rxrundisp_i | std_logic_vector ( 3 downto 0 ) |
| mgtB_rxrundisp_i | std_logic_vector ( 3 downto 0 ) |
| mgtA_rxnotintable_i | std_logic_vector ( 3 downto 0 ) |
| mgtB_rxnotintable_i | std_logic_vector ( 3 downto 0 ) |
| mgtA_rxdisperr_i | std_logic_vector ( 3 downto 0 ) |
| mgtB_rxdisperr_i | std_logic_vector ( 3 downto 0 ) |
| rxA_error_i | std_logic |
| rxB_error_i | std_logic |
| destination_aligned_i | std_logic := ' 0 ' |
| destination_counter_i | std_logic_vector ( 5 downto 0 ) := " 000000 " |
| tx_comma_init_i | std_logic := ' 1 ' |
| tx_ready_reg_i | std_logic |
| rxA_aligned_i | std_logic := ' 0 ' |
| rxB_aligned_i | std_logic := ' 0 ' |
| rx_ready_buff | std_logic := ' 1 ' |
| tx_A_package_state_i | std_logic_vector ( 1 downto 0 ) := " 00 " |
| tx_B_package_state_i | std_logic_vector ( 1 downto 0 ) := " 00 " |
| tx_A_crc_data_valid_i | std_logic := ' 1 ' |
| tx_B_crc_data_valid_i | std_logic := ' 1 ' |
| tx_A_crc_init_i | std_logic := ' 0 ' |
| tx_B_crc_init_i | std_logic := ' 0 ' |
| tx_A_send_comma_i | std_logic := ' 0 ' |
| tx_B_send_comma_i | std_logic := ' 0 ' |
| tx_A_send_crc_i | std_logic := ' 0 ' |
| tx_B_send_crc_i | std_logic := ' 0 ' |
| tx_send_idle_i | std_logic := ' 0 ' |
| rxA_package_state_i | std_logic_vector ( 1 downto 0 ) := " 00 " |
| rxA_crc_data_valid_i | std_logic := ' 1 ' |
| rxA_crc_init_i | std_logic := ' 0 ' |
| rxA_crc_value_i | std_logic_vector ( 31 downto 0 ) |
| rxB_package_state_i | std_logic_vector ( 1 downto 0 ) := " 00 " |
| rxB_crc_data_valid_i | std_logic := ' 1 ' |
| rxB_crc_init_i | std_logic := ' 0 ' |
| rxB_crc_value_i | std_logic_vector ( 31 downto 0 ) |
| rxA_data_ready_i | std_logic |
| rxB_data_ready_i | std_logic |
| rxA_data_error_i | std_logic |
| rxB_data_error_i | std_logic |
| mgtA_control_out_i | std_logic_vector ( 3 downto 0 ) |
| mgtB_control_out_i | std_logic_vector ( 3 downto 0 ) |
| mgtA_eop_out_i | std_logic |
| mgtB_eop_out_i | std_logic |
| mgtA_data_ready_out_i | std_logic |
| mgtB_data_ready_out_i | std_logic |
| mgtA_data_error_out_i | std_logic |
| mgtB_data_error_out_i | std_logic |
| mgtA_package_ok_out_i | std_logic |
| mgtB_package_ok_out_i | std_logic |
Component Instantiations | |
| drp_clk_in_bufr_i | BUFR |
| CLK_BUFFER_A | BUFR |
| reset_A_TX_I_inst | sata_GT11_INIT_TX <Entity sata_GT11_INIT_TX> |
| reset_B_TX_I_inst | sata_GT11_INIT_TX <Entity sata_GT11_INIT_TX> |
| reset_A_RX_I_inst | sata_GT11_INIT_RX <Entity sata_GT11_INIT_RX> |
| reset_B_RX_I_inst | sata_GT11_INIT_RX <Entity sata_GT11_INIT_RX> |
| rocketio_sata_i | ROCKETIO_SATA <Entity ROCKETIO_SATA> |
Detailed Description
SATA wrapper.Definition at line 92 of file sata.vhd.
Member Data Documentation
ROCKETIO_SATA [Component] |
The documentation for this class was generated from the following file:
