ddr2_usr_be Entity Reference
top module of DDR2 RAM controller More...
Inheritance diagram for ddr2_usr_be:
Collaboration diagram for ddr2_usr_be:
Architectures | |
| ddr2_usr_be_arc | Architecture |
| top module of DDR2 RAM controller More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| unisim | |
| Library with Xilinx primitives. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_arith | |
| arithmetic operations on std_logic datatypes, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
| vcomponents | |
| Header with Xilinx primitives. | |
Ports | |
| cntrl0_DDR2_DQ | inout std_logic_vector ( 63 downto 0 ) |
| Data to/from SDRAM. | |
| cntrl0_DDR2_DQS | inout std_logic_vector ( 7 downto 0 ) |
| Differential data strobe, pos. | |
| cntrl0_DDR2_DQS_N | inout std_logic_vector ( 7 downto 0 ) |
| Differential data strobe, neg. | |
| cntrl0_DDR2_A | out std_logic_vector ( 13 downto 0 ) |
| Address. | |
| cntrl0_DDR2_BA | out std_logic_vector ( 1 downto 0 ) |
| Bank address. | |
| cntrl0_DDR2_RAS_N | out std_logic |
| Row address select. | |
| cntrl0_DDR2_CAS_N | out std_logic |
| Column address select. | |
| cntrl0_DDR2_WE_N | out std_logic |
| Write enable. | |
| cntrl0_DDR2_RESET_N | out std_logic |
| Reset. | |
| cntrl0_DDR2_CS_N | out std_logic |
| Chip select. | |
| cntrl0_DDR2_ODT | out std_logic |
| On-Die Termination. | |
| cntrl0_DDR2_CKE | out std_logic |
| Clock enable. | |
| cntrl0_DDR2_DM | out std_logic_vector ( 7 downto 0 ) |
| data mask | |
| cntrl0_DDR2_CK | out std_logic |
| Differential clock, pos. | |
| cntrl0_DDR2_CK_N | out std_logic |
| Differential clock, neg. | |
| COMP_OUT1 | out std_logic |
| debug | |
| COMP_OUT2 | out std_logic |
| debug | |
| LED_CONTR | out std_logic |
| debug | |
| LED_R | out std_logic |
| debug | |
| VALID_OUT | out std_logic |
| data valid | |
| SYSCLK | in std_logic |
| 200 MHz | |
| CLK_SLOW | in std_logic |
| Any clock slower than 100 MHz. | |
| R_W | in std_logic |
| R/W select, 1 = read, 0 = write. | |
| FETCH | out std_logic |
| Get write data from buffer. | |
| RESET_IN | in std_logic |
| Reset. | |
| ADDR_RES | in std_logic |
| Address counter reset. | |
| ADDR_OVR | out std_logic |
| Address counter overflow flag. | |
| DATA_IN | in std_logic_vector ( 127 downto 0 ) |
| Data in. | |
| EN | in std_logic |
| Enable. | |
| RDBURST_END | out std_logic |
| End of read burst flag. | |
| DATA_OUT | out std_logic_vector ( 127 downto 0 ) |
| Data out. | |
Detailed Description
top module of DDR2 RAM controllerThis entity is the top module of DDR2 RAM controller and provides the interface to the external SDRAM. It also takes care of the cyclic addressing scheme.
Definition at line 40 of file ddr2_usr_be.vhd.
Member Data Documentation
ADDR_OVR out std_logic [Port] |
ADDR_RES in std_logic [Port] |
CLK_SLOW in std_logic [Port] |
cntrl0_DDR2_A out std_logic_vector ( 13 downto 0 ) [Port] |
cntrl0_DDR2_BA out std_logic_vector ( 1 downto 0 ) [Port] |
cntrl0_DDR2_CAS_N out std_logic [Port] |
cntrl0_DDR2_CK out std_logic [Port] |
cntrl0_DDR2_CK_N out std_logic [Port] |
cntrl0_DDR2_CKE out std_logic [Port] |
cntrl0_DDR2_CS_N out std_logic [Port] |
cntrl0_DDR2_DM out std_logic_vector ( 7 downto 0 ) [Port] |
cntrl0_DDR2_DQ inout std_logic_vector ( 63 downto 0 ) [Port] |
cntrl0_DDR2_DQS inout std_logic_vector ( 7 downto 0 ) [Port] |
cntrl0_DDR2_DQS_N inout std_logic_vector ( 7 downto 0 ) [Port] |
cntrl0_DDR2_ODT out std_logic [Port] |
cntrl0_DDR2_RAS_N out std_logic [Port] |
cntrl0_DDR2_RESET_N out std_logic [Port] |
cntrl0_DDR2_WE_N out std_logic [Port] |
COMP_OUT1 out std_logic [Port] |
COMP_OUT2 out std_logic [Port] |
DATA_IN in std_logic_vector ( 127 downto 0 ) [Port] |
DATA_OUT out std_logic_vector ( 127 downto 0 ) [Port] |
EN in std_logic [Port] |
FETCH out std_logic [Port] |
ieee library [Library] |
standard IEEE library
Reimplemented in main_components.
Definition at line 24 of file ddr2_usr_be.vhd.
LED_CONTR out std_logic [Port] |
LED_R out std_logic [Port] |
R_W in std_logic [Port] |
RDBURST_END out std_logic [Port] |
RESET_IN in std_logic [Port] |
std_logic_1164 package [Package] |
std_logic definitions, see file
Reimplemented in main_components.
Definition at line 26 of file ddr2_usr_be.vhd.
std_logic_arith package [Package] |
arithmetic operations on std_logic datatypes, see file
Definition at line 28 of file ddr2_usr_be.vhd.
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 30 of file ddr2_usr_be.vhd.
SYSCLK in std_logic [Port] |
unisim library [Library] |
VALID_OUT out std_logic [Port] |
vcomponents package [Package] |
The documentation for this class was generated from the following file:
