Components | |
wrapped_bcm_emac_fifo_rx | |
FIFO IP core. | |
Component Instantiations | |
U0 | wrapped_bcm_emac_fifo_rx |
Read & write clocks need to be at specified values for FIFO status flags to function properly.
Definition at line 87 of file bcm_emac_fifo_rx.vhd.
wrapped_bcm_emac_fifo_rx [Component] |