RIO Entity Reference
RocketIO wrapper. More...
Inheritance diagram for RIO:
Collaboration diagram for RIO:
Architectures | |
| RIO_arc | Architecture |
| Instantiation of RocketIO primitive. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| unisim | |
| Library with Xilinx primitives. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| numeric_std | |
| arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
| vcomponents | |
| Header with Xilinx primitives. | |
Generics | |
| SIMULATION_P | integer := 0 |
| Set to 1 when using module in simulation. | |
| TX_FD_MIN_P | std_logic_vector ( 10 downto 0 ) := " 00000011101 " |
| Floor (128*Ttxoutclk1/Tdclk) - 3. | |
| TX_FD_EN_P | std_logic := ' 1 ' |
| 1 = enable calblock TX frequency test | |
| RX_FD_MIN_P | std_logic_vector ( 10 downto 0 ) := " 00000011101 " |
| Floor (128*Trxrecclk1/Tdclk) - 3. | |
| RX_FD_EN_P | std_logic := ' 1 ' |
| 1 = enable calblock RX frequency test | |
| TX_FD_WIDTH_P | integer := 11 |
| TX Fdetect MIN value width. | |
| RX_FD_WIDTH_P | integer := 11 |
| RX Fdetect MIN value width. | |
| MGT0_GT11_MODE_P | string := " b " |
| Default Location. | |
| MGT0_MGT_ID_P | integer := 1 |
| 0=A, 1=B | |
Ports | |
| MGT0_ACTIVE_OUT | out std_logic |
| MGT0_DISABLE_IN | in std_logic |
| MGT0_DRP_RESET_IN | in std_logic |
| MGT0_RX_SIGNAL_DETECT_IN | in std_logic |
| MGT0_TX_SIGNAL_DETECT_IN | in std_logic |
| MGT0_DCLK_IN | in std_logic |
| MGT0_POWERDOWN_IN | in std_logic |
| MGT0_TXINHIBIT_IN | in std_logic |
| MGT0_RXLOCK_OUT | out std_logic |
| MGT0_TXLOCK_OUT | out std_logic |
| MGT0_RXPOLARITY_IN | in std_logic |
| MGT0_TXPOLARITY_IN | in std_logic |
| MGT0_COMBUSIN_IN | in std_logic_vector ( 15 downto 0 ) |
| MGT0_COMBUSOUT_OUT | out std_logic_vector ( 15 downto 0 ) |
| MGT0_RXDATA_OUT | out std_logic_vector ( 31 downto 0 ) |
| MGT0_REFCLK1_IN | in std_logic |
| MGT0_RXPMARESET_IN | in std_logic |
| MGT0_RXRESET_IN | in std_logic |
| MGT0_TXPMARESET_IN | in std_logic |
| MGT0_TXRESET_IN | in std_logic |
| MGT0_RX1N_IN | in std_logic |
| MGT0_RX1P_IN | in std_logic |
| MGT0_TX1N_OUT | out std_logic |
| MGT0_TX1P_OUT | out std_logic |
| MGT0_RXSTATUS_OUT | out std_logic_vector ( 5 downto 0 ) |
| MGT0_RXSYNC_IN | in std_logic |
| MGT0_TXSYNC_IN | in std_logic |
| MGT0_TXDATA_IN | in std_logic_vector ( 31 downto 0 ) |
| MGT0_RXRECCLK1_OUT | out std_logic |
| MGT0_RXRECCLK2_OUT | out std_logic |
| MGT0_RXUSRCLK2_IN | in std_logic |
| MGT0_TXOUTCLK1_OUT | out std_logic |
| MGT0_TXOUTCLK2_OUT | out std_logic |
| MGT0_TXUSRCLK2_IN | in std_logic |
Detailed Description
RocketIO wrapper.
RocketIO wrapper generated by RocketIO Wizard v1.2. Block diagram and internal clocking scheme is shown below:
Definition at line 63 of file rio.vhd.
Member Data Documentation
MGT0_GT11_MODE_P string := " b " [Generic] |
MGT0_MGT_ID_P integer := 1 [Generic] |
numeric_std package [Package] |
RX_FD_EN_P std_logic := ' 1 ' [Generic] |
RX_FD_MIN_P std_logic_vector ( 10 downto 0 ) := " 00000011101 " [Generic] |
RX_FD_WIDTH_P integer := 11 [Generic] |
SIMULATION_P integer := 0 [Generic] |
std_logic_1164 package [Package] |
TX_FD_EN_P std_logic := ' 1 ' [Generic] |
TX_FD_MIN_P std_logic_vector ( 10 downto 0 ) := " 00000011101 " [Generic] |
TX_FD_WIDTH_P integer := 11 [Generic] |
vcomponents package [Package] |
The documentation for this class was generated from the following file:
