main_components Package Reference
Declaration of all major components, global constants & types. More...
Inheritance diagram for main_components:
Collaboration diagram for main_components:
Libraries | |
| ieee | |
| standard IEEE library | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
Components | |
| clocks | <Entity clocks> |
| Main clock module. | |
| rio2mem | <Entity rio2mem> |
| Main design components. | |
| delay | <Entity delay> |
| Delay unit. | |
| edge | <Entity edge> |
| Edge detection, rising. | |
| edge_fal | <Entity edge_fal> |
| Edge detection, falling. | |
| busy | <Entity busy> |
| Busy module. | |
| rios_all | <Entity rios_all> |
| DAQ-RocketIO top module. | |
| ddr_data_buffer | <Entity ddr_data_buffer> |
| Buffer between RocketIOs & DDR RAM. | |
| ram_user_backend | <Entity ram_user_backend> |
| DDR RAM top module. | |
| ddr2_data_buffer | <Entity ddr2_data_buffer> |
| Buffer between RocketIOs & DDR2 RAM. | |
| ddr2_usr_be | <Entity ddr2_usr_be> |
| DDR RAM top module. | |
| eth_buf | <Entity eth_buf> |
| Buffer between DDR2 & EMAC. | |
| ethernet_top | <Entity ethernet_top> |
| EMAC top module. | |
| cnt_ddr2_rd | <Entity cnt_ddr2_rd> |
| Counter for DDR2 accesses. | |
| cnt_ddr_rd | <Entity cnt_ddr_rd> |
| Counter for DDR accesses. | |
| lvl1_buf | <Entity lvl1_buf> |
| BRAM buffer for TDAQ data. | |
| l1a_fifo | <Entity l1a_fifo> |
| FIFO for L1As. | |
| rio_or | <Entity rio_or> |
| delta_t_ac_top | <Entity delta_t_ac_top> |
| Time-windows & coincidences. | |
| intime | <Entity intime> |
| in-time (collision) time cut | |
| extend_test | <Entity extend_test> |
| Extend pulses. | |
| ddr_eth_buf | <Entity ddr_eth_buf> |
| Buffer between DDR & EMAC. | |
| icon | <Entity icon> |
| Chipscope controller. | |
| ila | |
| Chipscope probe. | |
| lcd_controller | <Entity lcd_controller> |
| LCD top module. | |
| prescaler | <Entity prescaler> |
| Frequency divider. | |
| LCD | <Entity LCD> |
| LCD controller. | |
| bcm_rod | <Entity bcm_rod> |
| ROD top module. | |
| ltp_comm | <Entity ltp_comm> |
| LTP interface module. | |
| riocheck | <Entity riocheck> |
| RocketIO monitor. | |
| side_4rios | <Entity side_4rios> |
| 4 DAQ-RocketIOs | |
| ddr2_chksum_cal | <Entity ddr2_chksum_cal> |
| Checksum calculation for DDR2 RAM. | |
| ddr_chksum_cal | <Entity ddr_chksum_cal> |
| Checksum calculation for DDR RAM. | |
| sata | <Entity sata> |
| SATA top module. | |
| command_decoder | <Entity command_decoder> |
| decoder for commands from PC | |
| dss_comm | <Entity dss_comm> |
| DSS interface module. | |
| cibu_comm | <Entity cibu_comm> |
| CIBU interface module. | |
| ctp_comm | <Entity ctp_comm> |
| CTP interface module. | |
| raw_data_emul | <Entity raw_data_emul> |
| raw data pattern generator | |
| proc_data_emul | <Entity proc_data_emul> |
| proc data pattern generator | |
| status_collector | <Entity status_collector> |
| data collector for DCS status messages | |
| tdaq_collector | <Entity tdaq_collector> |
| data collector for tdaq status messages | |
| statistics | <Entity statistics> |
| Statistics module. | |
| ctp_logic | <Entity ctp_logic> |
| CTP logic. | |
| bcm_signal_delay | <Entity bcm_signal_delay> |
| flexible 1 bit delay module | |
| bcm_signal_delay_vec | <Entity bcm_signal_delay_vec> |
| flexible 32 bit delay module | |
| incrementer | <Entity incrementer> |
| increment counter | |
| bridge | <Entity bridge> |
| SATA wrapper with separate channels. | |
| abort_controller | <Entity abort_controller> |
| beam abort logic | |
| BID_cnt | <Entity BID_cnt> |
| Bunch counter for BCID. | |
| pmdelay | <Entity pmdelay> |
| delay for post mortem | |
| generic_shift_reg | <Entity generic_shift_reg> |
| generic shift register | |
Constants | |
| gnd | std_logic := ' 0 ' |
| gnd_vec | std_logic_vector ( 7 downto 0 ) := ( others = > gnd ) |
| gnd_vec_long | std_logic_vector ( 99 downto 0 ) := ( others = > gnd ) |
Types | |
| global_states | ( g_waitriostartup , g_calib , g_idle , g_capture , g_reset , g_read , g_error , g_freeze , g_armed ) |
| lcd_line | array ( 0 to 15 ) of std_logic_vector ( 7 downto 0 ) |
| lcd_states | ( lcdinit , lcdwrite ) |
| read_out_states | ( r_idle , r_proc , r_raw , r_int , r_err ) |
| emac_states | ( e_idle , e_dump , e_stat , e_ack , e_fillstat , e_tdaq , e_filltdaq ) |
| err_states | ( err_no , err_yes ) |
Detailed Description
Declaration of all major components, global constants & types.Definition at line 31 of file main_components.vhd.
Member Data Documentation
abort_controller [Component] |
bcm_rod [Component] |
bcm_signal_delay [Component] |
bcm_signal_delay_vec [Component] |
BID_cnt [Component] |
Bunch counter for BCID.
Reimplemented from ltp_comm.ltp_comm_arc.
Definition at line 1634 of file main_components.vhd.
bridge [Component] |
busy [Component] |
cibu_comm [Component] |
clocks [Component] |
cnt_ddr2_rd [Component] |
cnt_ddr_rd [Component] |
command_decoder [Component] |
ctp_comm [Component] |
ctp_logic [Component] |
ddr2_chksum_cal [Component] |
Checksum calculation for DDR2 RAM.
Reimplemented from status_collector.status_collector_arc.
Definition at line 1027 of file main_components.vhd.
ddr2_data_buffer [Component] |
ddr2_usr_be [Component] |
ddr_chksum_cal [Component] |
ddr_data_buffer [Component] |
ddr_eth_buf [Component] |
delay [Component] |
delta_t_ac_top [Component] |
dss_comm [Component] |
edge [Component] |
Edge detection, rising.
Reimplemented from busy.busy_arc.
Definition at line 242 of file main_components.vhd.
edge_fal [Component] |
eth_buf [Component] |
ethernet_top [Component] |
extend_test [Component] |
Extend pulses.
Reimplemented from ddr2_usr_be.ddr2_usr_be_arc.
Definition at line 736 of file main_components.vhd.
generic_shift_reg [Component] |
icon [Component] |
ieee library [Library] |
standard IEEE library
Reimplemented from abort_controller.
Definition at line 26 of file main_components.vhd.
ila [Component] |
incrementer [Component] |
intime [Component] |
l1a_fifo [Component] |
LCD [Component] |
lcd_controller [Component] |
ltp_comm [Component] |
lvl1_buf [Component] |
pmdelay [Component] |
prescaler [Component] |
Frequency divider.
Reimplemented from clocks.coldplay.
Definition at line 804 of file main_components.vhd.
proc_data_emul [Component] |
ram_user_backend [Component] |
raw_data_emul [Component] |
rio2mem [Component] |
rio_or [Component] |
riocheck [Component] |
rios_all [Component] |
sata [Component] |
SATA top module.
Reimplemented from bridge.bridge_arc.
Definition at line 1055 of file main_components.vhd.
side_4rios [Component] |
statistics [Component] |
status_collector [Component] |
std_logic_1164 package [Package] |
std_logic definitions, see file
Reimplemented from abort_controller.
Definition at line 28 of file main_components.vhd.
tdaq_collector [Component] |
The documentation for this class was generated from the following file:
