rio2mem.rio2mem_arc Architecture Reference

Contains all major design modules (RAMs, RIO, EMAC). More...

Inheritance diagram for rio2mem.rio2mem_arc:

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Collaboration diagram for rio2mem.rio2mem_arc:

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List of all members.


Processes

count_coins  ( BCLK )
 count in-time coincidences
count_backa  ( BCLK )
 count out-of-time coincidences A
count_backc  ( BCLK )
 count out-of-time coincidences C
count_ch1  ( BCLK )
 count hits ch1
count_ch2  ( BCLK )
 count hits ch2
count_ch3  ( BCLK )
 count hits ch3
count_ch4  ( BCLK )
 count hits ch4
count_ch5  ( BCLK )
 count hits ch5
count_ch6  ( BCLK )
 count hits ch6
count_ch7  ( BCLK )
 count hits ch7
count_ch8  ( BCLK )
 count hits ch8
sw_to_err  ( REFCLK_P , RESET )
 switch to sending of error message
readout_controller_fsm  ( REFCLK_P )
 readout control FSM
shift_clear_ddr2  ( REFCLK_P )
 shift mem_reset by 5 clk cycles to start clear of eth buffers
shift_clear_ddr  ( BCLK4X_P )
 shift mem_reset by 5 clk cycles to start clear of eth buffers
readout_controller_proc  ( BCLK4X_P )
 DDR RAM.
overflow_flag_proc  ( BCLK4X_P , mem_reset )
 produce buffer overflow flag
readout_controller_raw  ( REFCLK_P )
 control FSM for DDR2
overflow_flag_raw  ( REFCLK_P , mem_reset )
 produce buffer overflow flag
set_second_active  ( EMAC_CLK , RESET )
 register 1Hz frequency
set_tdaq_active  ( EMAC_CLK , RESET )
 register TDAQ status request
emac_manager  ( EMAC_CLK , RESET )
 FSM to manage access to EMAC.
pktdone_rsff  ( EMAC_CLK )
 set/reset pktdone signal
ackvld_rsff  ( EMAC_CLK )
 set/reset ack_vld signal
start_pkt_rsff  ( EMAC_CLK )
 set/reset start_pkt signal
stat_pkt_rsff  ( EMAC_CLK )
 set/reset stat_pkt signal
tdaq_pkt_rsff  ( EMAC_CLK )
 set/reset tdaq_pkt signal
start  ( CLK_HZ , RESET )
 ARP announcement after reboot.
en_arp  ( EMAC_CLK , RESET )
 ARP announcement after reboot.
busy_ext_latch  ( EMAC_CLK , RESET )
 latch busy from TDAQ software
toggle_data_generation  ( EMAC_CLK , RESET )
 switch internal data generation on and off
empty_flag  ( BCLK , lvl1_buf_res )
l1adone_latch  ( BCLK , RESET )
 wait with next l1a until rod formatter is ready
l1adone_latch1  ( BCLK , RESET )
 wait with next l1a until rod formatter is ready, signaling end of last burst
nllatches  ( BCLK )
 get falling edge
l1a_fifo_buffer_interface  ( BCLK , RESET )
 interface logic between L1A fifo and Level-1 data buffer
dss_alarm_latch  ( BCLK , RESET )
trigger_rate_1  ( BCLK , RESET )
 trigger rates
trigger_rate_2  ( BCLK , RESET )
 trigger rates
trigger_rate_3  ( BCLK , RESET )
 trigger rates
trigger_rate_4  ( BCLK , RESET )
 trigger rates
trigger_rate_5  ( BCLK , RESET )
 trigger rates
trigger_rate_6a  ( BCLK , RESET )
 trigger rates
trigger_rate_7a  ( BCLK , RESET )
 trigger rates
trigger_rate_8a  ( BCLK , RESET )
 trigger rates
trigger_rate_6c  ( BCLK , RESET )
 trigger rates
trigger_rate_7c  ( BCLK , RESET )
 trigger rates
trigger_rate_8c  ( BCLK , RESET )
 trigger rates
beam_permit_latch  ( BCLK , RESET )
inj_permit_latch  ( BCLK , RESET )

Constants

pattern  std_logic_vector ( 127 downto 0 ) := x " f0f0f0f0_f0f0f0f0_f0f0f0f0_f0f0f0f0 "
c_colwinl  std_logic_vector ( 5 downto 0 ) := conv_std_logic_vector ( 36 , 6 )
c_colwinh  std_logic_vector ( 5 downto 0 ) := conv_std_logic_vector ( 40 , 6 )
c_colwinlw  std_logic_vector ( 5 downto 0 ) := conv_std_logic_vector ( 28 , 6 )
c_colwinhw  std_logic_vector ( 5 downto 0 ) := conv_std_logic_vector ( 58 , 6 )
c_colwinlo1  std_logic_vector ( 5 downto 0 ) := conv_std_logic_vector ( 4 , 6 )
c_colwinho1  std_logic_vector ( 5 downto 0 ) := conv_std_logic_vector ( 8 , 6 )
c_colwinlo2  std_logic_vector ( 5 downto 0 ) := conv_std_logic_vector ( 4 , 6 )
c_colwinho2  std_logic_vector ( 5 downto 0 ) := conv_std_logic_vector ( 8 , 6 )

Signals

cs  read_out_states
ems  emac_states := e_idle
ddr2_clk  std_logic := ' 0 '
emac_clk_buf  std_logic := ' 0 '
ctor_clk  std_logic := ' 0 '
chkclk_r  std_logic := ' 0 '
chkclk_p  std_logic := ' 0 '
rios_work  std_logic := ' 0 '
fetch_proc  std_logic := ' 0 '
en_proc  std_logic := ' 0 '
en_cnt_proc  std_logic := ' 0 '
en_rd_proc  std_logic := ' 0 '
empty_proc  std_logic := ' 0 '
rw_proc_i  std_logic := ' 0 '
proc_vld  std_logic := ' 0 '
fetch_raw  std_logic := ' 0 '
en_raw  std_logic := ' 0 '
en_cnt_raw  std_logic := ' 0 '
en_rd_raw  std_logic := ' 0 '
empty_raw  std_logic := ' 0 '
rw_raw_i  std_logic := ' 0 '
raw_vld  std_logic := ' 0 '
burstind_raw  std_logic := ' 0 '
burstind_proc  std_logic := ' 0 '
fetch_int  std_logic := ' 0 '
fetch_int_latch  std_logic := ' 0 '
get_eth_byte  std_logic := ' 0 '
fetch_raw_eth  std_logic := ' 0 '
fetch_proc_eth  std_logic := ' 0 '
fetch_int_eth  std_logic := ' 0 '
wr_eth_buf_int  std_logic := ' 0 '
wr_buf_raw  std_logic := ' 0 '
wr_buf_proc  std_logic := ' 0 '
wr_buf_raw_i  std_logic := ' 0 '
wr_buf_proc_i  std_logic := ' 0 '
datatype_i  std_logic := ' 0 '
mem_reset  std_logic := ' 0 '
mem_reset_short  std_logic := ' 0 '
trans_complete  std_logic := ' 0 '
proc_trans_complete  std_logic := ' 0 '
raw_trans_complete  std_logic := ' 0 '
pkt_full  std_logic := ' 0 '
pktdone  std_logic := ' 0 '
start_rdout  std_logic := ' 0 '
start_rdout_ext  std_logic := ' 0 '
rios_ready_i  std_logic := ' 0 '
clr_ddr  std_logic := ' 0 '
clr_ddr2  std_logic := ' 0 '
clear_raw  std_logic := ' 0 '
clear_int  std_logic := ' 0 '
clear_proc  std_logic := ' 0 '
wr_buf_int  std_logic := ' 0 '
ethbufres_proc  std_logic := ' 0 '
ethbufres_raw  std_logic := ' 0 '
ethbufres_int  std_logic := ' 0 '
ethbufres_proc_i  std_logic := ' 0 '
ethbufres_raw_i  std_logic := ' 0 '
ethbufres_int_i  std_logic := ' 0 '
delta_vld_a  std_logic := ' 0 '
delta_vld_backa  std_logic := ' 0 '
delta_vld_backc  std_logic := ' 0 '
delta_vld2_a  std_logic := ' 0 '
delta_vld_b  std_logic := ' 0 '
delta_vld2_b  std_logic := ' 0 '
delta_vld_c  std_logic := ' 0 '
delta_vld2_c  std_logic := ' 0 '
delta_vld_d  std_logic := ' 0 '
delta_vld2_d  std_logic := ' 0 '
data_rod_vld  std_logic := ' 0 '
data_rod_vld_i  std_logic := ' 0 '
cal_irena_i  std_logic := ' 0 '
cal_ewa_i  std_logic := ' 0 '
cal_andrej_i  std_logic := ' 0 '
cal_heinz_i  std_logic := ' 0 '
cal_marko_i  std_logic := ' 0 '
cal_william_i  std_logic := ' 0 '
cal_harris_i  std_logic := ' 0 '
cal_helmut_i  std_logic := ' 0 '
err_msg_complete  std_logic := ' 0 '
eth_en_i  std_logic := ' 0 '
err_eth_en_i  std_logic := ' 0 '
fetch_err_eth  std_logic := ' 0 '
swtoerr_i  std_logic := ' 0 '
swtoerr_ff  std_logic := ' 0 '
over_proc_i  std_logic := ' 0 '
over_raw_i  std_logic := ' 0 '
raw_cnt_reset  std_logic := ' 0 '
proc_cnt_reset  std_logic := ' 0 '
en_riomonitor  std_logic := ' 0 '
pkt_rddone_proc  std_logic := ' 0 '
pkt_rddone_raw  std_logic := ' 0 '
pkt_rddone_proc1  std_logic := ' 0 '
pkt_rddone_raw1  std_logic := ' 0 '
get_raw_chksum  std_logic := ' 0 '
get_proc_chksum  std_logic := ' 0 '
get_chksum  std_logic := ' 0 '
sata_tx_a_lock_i  std_logic := ' 0 '
sata_tx_b_lock_i  std_logic := ' 0 '
sata_rx_a_lock_i  std_logic := ' 0 '
sata_rx_b_lock_i  std_logic := ' 0 '
sata_tx_a_ready_i  std_logic := ' 0 '
sata_rx_a_ready_i  std_logic := ' 0 '
sata_tx_b_ready_i  std_logic := ' 0 '
sata_rx_b_ready_i  std_logic := ' 0 '
sata_data_ready_i  std_logic := ' 0 '
sata_data_vld_a  std_logic := ' 0 '
sata_error_a  std_logic := ' 0 '
sata_data_vld_b  std_logic := ' 0 '
sata_error_b  std_logic := ' 0 '
sata_error_clk_i  std_logic := ' 0 '
sata_eop_generate_i  std_logic := ' 0 '
sata_eop_received_i  std_logic := ' 0 '
sata_package_ok_i  std_logic := ' 0 '
sata_data_send_i  std_logic := ' 0 '
sata_data_clk  std_logic := ' 0 '
sata_listening_a  std_logic := ' 0 '
sata_listening_b  std_logic := ' 0 '
sata_package_good_a  std_logic := ' 0 '
sata_package_good_b  std_logic := ' 0 '
sata_package_bad_a  std_logic := ' 0 '
sata_package_bad_b  std_logic := ' 0 '
sata_ok_i  std_logic := ' 0 '
sl_trig_pc  std_logic := ' 0 '
sl_trig_pc_i  std_logic := ' 0 '
sl_trig_pc_ii  std_logic := ' 0 '
sl_pause  std_logic := ' 0 '
sl_pause_i  std_logic := ' 0 '
sl_pause_ii  std_logic := ' 0 '
buf_pause  std_logic := ' 0 '
res_pc_i  std_logic := ' 0 '
pc_cmdvld  std_logic := ' 0 '
stop_pc_i  std_logic := ' 0 '
trig_pc_i  std_logic := ' 0 '
fill_buf_i  std_logic := ' 0 '
start_run  std_logic := ' 0 '
start_run_i  std_logic := ' 0 '
start_run_ii  std_logic := ' 0 '
dss_ab_i  std_logic := ' 0 '
dss_w_i  std_logic := ' 0 '
dss_ab_ii  std_logic := ' 0 '
dss_w_ii  std_logic := ' 0 '
b_perm_i  std_logic := ' 0 '
i_perm_i  std_logic := ' 0 '
b_perm_ii  std_logic := ' 0 '
i_perm_ii  std_logic := ' 0 '
lvl1_buf_res  std_logic := ' 0 '
rate_block  std_logic := ' 0 '
pat_fill  std_logic := ' 0 '
en_fill  std_logic := ' 0 '
arp_i  std_logic := ' 0 '
arp_ii  std_logic := ' 0 '
arp_done  std_logic := ' 0 '
mac_lock_i  std_logic := ' 0 '
rd_rdy_i  std_logic := ' 0 '
busy_ext  std_logic := ' 1 '
busy_ext_rs  std_logic := ' 0 '
busy_i  std_logic := ' 0 '
run_num_en  std_logic := ' 0 '
ev_type_en  std_logic := ' 0 '
rd_ovr  std_logic := ' 0 '
rd_ovr_i  std_logic := ' 0 '
rate_reset  std_logic := ' 0 '
rate_reset_i  std_logic := ' 0 '
get_stats  std_logic := ' 0 '
srcid_en  std_logic := ' 0 '
algosel_en  std_logic := ' 0 '
mask_en  std_logic := ' 0 '
second  std_logic := ' 0 '
second_active  std_logic := ' 0 '
stat_msg_done  std_logic := ' 0 '
inc_pktnr  std_logic := ' 0 '
ack_vld  std_logic := ' 0 '
fetch_stat_eth  std_logic := ' 0 '
fetch_tdaq_eth  std_logic := ' 0 '
get_stat_chksum  std_logic := ' 0 '
get_tdaq_chksum  std_logic := ' 0 '
start_pkt  std_logic := ' 0 '
start_nxt  std_logic := ' 0 '
start_nxt_st  std_logic := ' 0 '
start_stat  std_logic := ' 0 '
start_pkt_ff  std_logic := ' 0 '
pktdone_ff  std_logic := ' 0 '
ack_vld_ff  std_logic := ' 0 '
en_mem  std_logic := ' 0 '
en_stat_mac  std_logic := ' 0 '
assemb_stat  std_logic := ' 0 '
stat_asm_done_i  std_logic := ' 0 '
en_stat_mac_set  std_logic := ' 0 '
stat_msg_rd_done  std_logic := ' 0 '
tdaq_asm_done_i  std_logic := ' 0 '
en_tdaq_mac_set  std_logic := ' 0 '
tdaq_msg_rd_done  std_logic := ' 0 '
read_out_i  std_logic := ' 0 '
set_ctp  std_logic := ' 0 '
set_ctp_i  std_logic := ' 0 '
set_dss_ab_i  std_logic := ' 0 '
set_dss_w_i  std_logic := ' 0 '
set_dss_warning  std_logic := ' 0 '
set_dss_abort  std_logic := ' 0 '
set_injection_permit  std_logic := ' 0 '
set_beam_permit  std_logic := ' 0 '
dss_warning  std_logic := ' 0 '
dss_abort  std_logic := ' 0 '
injection_permit  std_logic := ' 0 '
beam_permit  std_logic := ' 0 '
set_ecr_load_i  std_logic := ' 0 '
set_l1a_load_i  std_logic := ' 0 '
set_i_perm  std_logic := ' 0 '
set_b_perm  std_logic := ' 0 '
lf_empty  std_logic := ' 1 '
lf_full  std_logic := ' 0 '
lf_rden  std_logic := ' 0 '
lf_rden2  std_logic := ' 0 '
lf_wren  std_logic := ' 0 '
lf_wren_i  std_logic := ' 0 '
lf_wren_ii  std_logic := ' 0 '
l1a_done  std_logic := ' 0 '
bcr_i  std_logic := ' 0 '
ecr_i  std_logic := ' 0 '
l1a_del  std_logic := ' 0 '
l1a_i  std_logic := ' 0 '
l1a_ii  std_logic := ' 0 '
l1a_inc  std_logic := ' 0 '
lvl1_buf_rden  std_logic := ' 0 '
fpgaid_en  std_logic := ' 0 '
format_ver_en  std_logic := ' 0 '
ecr_force  std_logic := ' 0 '
bcr_force  std_logic := ' 0 '
force_bcr_i  std_logic := ' 0 '
force_ecr_i  std_logic := ' 0 '
l1a_force  std_logic := ' 0 '
l1a_force_i  std_logic := ' 0 '
l1a_force_ii  std_logic := ' 0 '
busy_clr  std_logic := ' 0 '
ctp_src_i  std_logic := ' 0 '
ctp_src_ii  std_logic := ' 0 '
ctp_src_en  std_logic := ' 0 '
orbit_load_en  std_logic := ' 0 '
send_tdaq_status  std_logic := ' 0 '
set_orbit  std_logic := ' 0 '
dcs_errflag  std_logic := ' 0 '
sl_lff_i  std_logic := ' 1 '
 default to 1!!!
sl_ldown_i  std_logic := ' 1 '
 default to 1!!!
next_l1a  std_logic := ' 1 '
 default to 1!!!
next_l1a1  std_logic := ' 0 '
get_next_l1a  std_logic := ' 0 '
nllatch1  std_logic := ' 0 '
nllatch2  std_logic := ' 0 '
dss_a_i  std_logic := ' 0 '
dss_ab1_i  std_logic := ' 0 '
dss_ab2_i  std_logic := ' 0 '
dss_wa_i  std_logic := ' 0 '
dss_wa1_i  std_logic := ' 0 '
dss_wa2_i  std_logic := ' 0 '
inj_p_i  std_logic := ' 0 '
inj_p1_i  std_logic := ' 0 '
inj_p2_i  std_logic := ' 0 '
bem_p_i  std_logic := ' 0 '
bem_p1_i  std_logic := ' 0 '
bem_p2_i  std_logic := ' 0 '
sata_dssw  std_logic := ' 0 '
sata_dssa  std_logic := ' 0 '
sata_iperm  std_logic := ' 0 '
sata_bperm  std_logic := ' 0 '
tdaq_active  std_logic := ' 0 '
tdaq_msg_done  std_logic := ' 0 '
assemb_tdaq  std_logic := ' 0 '
en_tdaq_mac  std_logic := ' 0 '
pktdone_long  std_logic := ' 0 '
rod_status_i  std_logic := ' 0 '
trig_del_en  std_logic := ' 0 '
ack_ok  std_logic := ' 0 '
ack_ok_simple  std_logic := ' 0 '
ack_miss  std_logic := ' 0 '
ack_err  std_logic := ' 0 '
orbit_del  std_logic := ' 0 '
inhib_del_en  std_logic := ' 0 '
mode_i  std_logic := ' 0 '
tty_src_i  std_logic := ' 0 '
tty_src_ii  std_logic := ' 0 '
tty_src_en  std_logic := ' 0 '
dssw_src_i  std_logic := ' 0 '
dssw_src_ii  std_logic := ' 0 '
dssw_src_en  std_logic := ' 0 '
dssa_src_i  std_logic := ' 0 '
dssa_src_ii  std_logic := ' 0 '
dssa_src_en  std_logic := ' 0 '
cibi_src_i  std_logic := ' 0 '
cibi_src_ii  std_logic := ' 0 '
cibi_src_en  std_logic := ' 0 '
cibb_src_i  std_logic := ' 0 '
cibb_src_ii  std_logic := ' 0 '
cibb_src_en  std_logic := ' 0 '
tty_en  std_logic := ' 0 '
input_en_status_b  std_logic := ' 0 '
rxl1  std_logic := ' 0 '
rxl2  std_logic := ' 0 '
rxl3  std_logic := ' 0 '
rxl4  std_logic := ' 0 '
rxl5  std_logic := ' 0 '
rxl6  std_logic := ' 0 '
rxl7  std_logic := ' 0 '
rxl8  std_logic := ' 0 '
txl1  std_logic := ' 0 '
txl2  std_logic := ' 0 '
txl3  std_logic := ' 0 '
txl4  std_logic := ' 0 '
txl5  std_logic := ' 0 '
txl6  std_logic := ' 0 '
txl7  std_logic := ' 0 '
txl8  std_logic := ' 0 '
rxr1  std_logic := ' 0 '
rxr2  std_logic := ' 0 '
rxr3  std_logic := ' 0 '
rxr4  std_logic := ' 0 '
rxr5  std_logic := ' 0 '
rxr6  std_logic := ' 0 '
rxr7  std_logic := ' 0 '
rxr8  std_logic := ' 0 '
txr1  std_logic := ' 0 '
txr2  std_logic := ' 0 '
txr3  std_logic := ' 0 '
txr4  std_logic := ' 0 '
txr5  std_logic := ' 0 '
txr6  std_logic := ' 0 '
txr7  std_logic := ' 0 '
txr8  std_logic := ' 0 '
en_edge_det  std_logic := ' 0 '
dump_beam  std_logic := ' 0 '
en_abort_contr  std_logic := ' 0 '
int_beam_permit  std_logic := ' 1 '
 default to '1' !!!
int_inj_permit  std_logic := ' 1 '
 default to '1' !!!
dss_alarm  std_logic := ' 0 '
dss_warn  std_logic := ' 0 '
SL_UWEN_i  std_logic := ' 0 '
latency_en  std_logic := ' 0 '
bcr_latency  std_logic := ' 0 '
end_slink_i  std_logic := ' 0 '
end_slink  std_logic := ' 0 '
ackw  std_logic := ' 0 '
acka  std_logic := ' 0 '
acki  std_logic := ' 0 '
ackb  std_logic := ' 0 '
ackw_ii  std_logic := ' 0 '
acka_ii  std_logic := ' 0 '
acki_ii  std_logic := ' 0 '
ackb_ii  std_logic := ' 0 '
sirena1_i  std_logic := ' 0 '
sewa1_i  std_logic := ' 0 '
sandrej1_i  std_logic := ' 0 '
sheinz1_i  std_logic := ' 0 '
smarko1_i  std_logic := ' 0 '
swilliam1_i  std_logic := ' 0 '
sharris1_i  std_logic := ' 0 '
shelmut1_i  std_logic := ' 0 '
sirena2_i  std_logic := ' 0 '
sewa2_i  std_logic := ' 0 '
sandrej2_i  std_logic := ' 0 '
sheinz2_i  std_logic := ' 0 '
smarko2_i  std_logic := ' 0 '
swilliam2_i  std_logic := ' 0 '
sharris2_i  std_logic := ' 0 '
shelmut2_i  std_logic := ' 0 '
sirena1_ii  std_logic := ' 0 '
sewa1_ii  std_logic := ' 0 '
sandrej1_ii  std_logic := ' 0 '
sheinz1_ii  std_logic := ' 0 '
smarko1_ii  std_logic := ' 0 '
swilliam1_ii  std_logic := ' 0 '
sharris1_ii  std_logic := ' 0 '
shelmut1_ii  std_logic := ' 0 '
sirena2_ii  std_logic := ' 0 '
sewa2_ii  std_logic := ' 0 '
sandrej2_ii  std_logic := ' 0 '
sheinz2_ii  std_logic := ' 0 '
smarko2_ii  std_logic := ' 0 '
swilliam2_ii  std_logic := ' 0 '
sharris2_ii  std_logic := ' 0 '
shelmut2_ii  std_logic := ' 0 '
latency_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
latency_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
SL_UD_i  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
high_gain_i  std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
low_gain_i  std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
rio_reset_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
rio_reset_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
tty_sel  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
dssw_sel  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
dssa_sel  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
cibi_sel  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
cibb_sel  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
cnt_ch1  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
cnt_ch2  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
cnt_ch3  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
cnt_ch4  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
cnt_ch5  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
cnt_ch6  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
cnt_ch7  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
cnt_ch8  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
cnt_coin  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
cnt_backa  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
cnt_backc  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
inhib_del_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
inhib_del_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
trig_del_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
trig_del_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
tty_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
tty_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
dss_a_iv  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
dss_wa_iv  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
inj_p_iv  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
bem_p_iv  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
lf_fullv  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
lf_emptyv  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
l1a_dispv  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
coarse_en  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
eth_debug  std_logic_vector ( 19 downto 0 ) := ( others = > ' 0 ' )
l1a_bid  std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
l1a_bid_in  std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
input_en_status_byte0  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
input_en_status_byte1  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
input_en_status_byte2  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
input_en_status_byte3  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
input_en_status_byte4  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
input_en_status_byte5  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
input_en_status_byte6  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
input_en_status_byte7  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
l1a_rate_i  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
sl_ldown_vec  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
sl_lff_vec  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
busy_vec  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
busy_ext_vec  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
input_en_status  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
input_en_status_rio  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ack  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
param_en_vec  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
mask_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 1 ' )
 default to 1!!!
mask_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
srcid_i  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
srcid_ii  std_logic_vector ( 23 downto 0 ) := ( others = > ' 0 ' )
algosel_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
algosel_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
run_num_i  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
run_num_ii  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ev_type_i  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ev_type_ii  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
set_orbit_val  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
orbit_load_i  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
orbit_load_ii  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ctp_sel  std_logic_vector ( 7 downto 0 ) := ( others = > ' 1 ' )
ctp_int  std_logic_vector ( 9 downto 1 ) := ( others = > ' 0 ' )
ctp_out  std_logic_vector ( 9 downto 1 ) := ( others = > ' 0 ' )
ctp_load  std_logic_vector ( 9 downto 1 ) := ( others = > ' 0 ' )
ctp_load_i  std_logic_vector ( 9 downto 1 ) := ( others = > ' 0 ' )
ctp_load_ii  std_logic_vector ( 9 downto 1 ) := ( others = > ' 0 ' )
ecr_load_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
l1a_load_i  std_logic_vector ( 23 downto 0 ) := ( others = > ' 0 ' )
ecr_load_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
l1a_load_ii  std_logic_vector ( 23 downto 0 ) := ( others = > ' 0 ' )
algo_data  std_logic_vector ( 191 downto 0 ) := ( others = > ' 0 ' )
proc_data_i  std_logic_vector ( 191 downto 0 ) := ( others = > ' 0 ' )
proc_data_ii  std_logic_vector ( 191 downto 0 ) := ( others = > ' 0 ' )
proc_data_i_emu  std_logic_vector ( 191 downto 0 ) := ( others = > ' 0 ' )
proc_data_lvl1  std_logic_vector ( 175 downto 0 ) := ( others = > ' 0 ' )
proc_data_ddr  std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
proc_data_eth  std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
proc_data_eth_i  std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
proc_data_eth_i_1  std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
raw_data_i  std_logic_vector ( 255 downto 0 ) := ( others = > ' 0 ' )
raw_data_ii  std_logic_vector ( 255 downto 0 ) := ( others = > ' 0 ' )
raw_data_i_emu  std_logic_vector ( 255 downto 0 ) := ( others = > ' 0 ' )
raw_data_ddr  std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' )
raw_data_eth  std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' )
raw_data_eth_i  std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' )
raw_data_eth_i_1  std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' )
raw_data_eth_i_2  std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' )
delta_t_a_i  std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
delta_t_b_i  std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
delta_t_c_i  std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
delta_t_d_i  std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
int_bufeth_in  std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
int_bufeth_in_i  std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
eth_byte  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
raw_byte  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
proc_byte  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
stat_byte  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
irena1_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ewa1_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
andrej1_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
heinz1_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
marko1_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
william1_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
harris1_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
helmut1_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
irena2_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ewa2_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
andrej2_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
heinz2_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
marko2_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
william2_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
harris2_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
helmut2_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
irena1_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ewa1_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
andrej1_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
heinz1_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
marko1_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
william1_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
harris1_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
helmut1_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
irena2_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ewa2_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
andrej2_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
heinz2_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
marko2_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
william2_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
harris2_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
helmut2_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
clr_shift  std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
clr_shift2  std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
a_i  std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
b_i  std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
data_rod  std_logic_vector ( 191 downto 0 ) := ( others = > ' 0 ' )
evid_i  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
l1a_evid  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
orbid_i  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ctp_tty_i  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
bcid_i  std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
bcid_long  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
mask_err_n_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 1 ' )
 default to '1'!!!
rioerr_type_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
proc_chksum_1  std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
proc_chksum_2  std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
tdaq_chksum  std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
stat_chksum  std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
raw_chksum_1  std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
chksum_1  std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
raw_chksum_2  std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
chksum_2  std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
sata_data_out_a  std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
sata_data_in_a  std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
sata_data_out_b  std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
sata_data_in_b  std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
sata_data_control_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
pc_cmd  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
pc_datatype  std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
tdaq_byte  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
en_adj_time  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
mult_irena_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
mult_ewa_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
mult_andrej_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
mult_heinz_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
mult_marko_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
mult_william_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
mult_harris_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
mult_helmut_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
mult_all  std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' )
data_src  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
hr_min_all  std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' )
hr_max_all  std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' )
hr_avg_all  std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' )
hr_avg_all_short  std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' )
l1a_fifo_fill  std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
fpgaid_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
fpgaid_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
format_ver_i  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
format_ver_ii  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
coarse0_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
coarse0_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
coarse1_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
coarse1_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
coarse2_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
coarse2_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
coarse3_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
coarse3_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
coarse4_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
coarse4_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
coarse5_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
coarse5_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
coarse6_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
coarse6_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
coarse7_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
coarse7_ii  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
fine_del_stdl_1  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
fine_del_stdl_2  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
fine_del_stdl_3  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
fine_del_stdl_4  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
fine_del_stdl_5  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
fine_del_stdl_6  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
fine_del_stdl_7  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
fine_del_stdl_0  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
err_code  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
rio_trip  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
cuts_en_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
colwinl  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
colwinh  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
colwinlw  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
colwinhw  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
colwinlo1  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
colwinho1  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
colwinlo2  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
colwinho2  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
colwinl_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
colwinh_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
colwinlw_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
colwinhw_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
colwinlo1_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
colwinho1_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
colwinlo2_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
colwinho2_i  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
rio_rx_locks  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
rio_tx_locks  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
rio_rx_rdys  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
rio_tx_rdys  std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
trig_rate_AttC  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
trig_rate_AttA  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
trig_rate_Mult3pC  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
trig_rate_Mult2C  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
trig_rate_Mult1C  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
trig_rate_Mult3pA  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
trig_rate_Mult2A  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
trig_rate_Mult1A  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
trig_rate_Wide  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
trig_rate_CtoA  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
trig_rate_AtoC  std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
numbunch_i  std_logic_vector ( 6 downto 0 ) := " 0000001 "
numbunch_ii  integer range 0 to 127 := 0
adj_time0  integer range 0 to 64 := 0
adj_time1  integer range 0 to 64 := 0
adj_time2  integer range 0 to 64 := 0
adj_time3  integer range 0 to 64 := 0
adj_time4  integer range 0 to 64 := 0
adj_time5  integer range 0 to 64 := 0
adj_time6  integer range 0 to 64 := 0
adj_time7  integer range 0 to 64 := 0
adj_time0i  integer range 0 to 64 := 0
adj_time1i  integer range 0 to 64 := 0
adj_time2i  integer range 0 to 64 := 0
adj_time3i  integer range 0 to 64 := 0
adj_time4i  integer range 0 to 64 := 0
adj_time5i  integer range 0 to 64 := 0
adj_time6i  integer range 0 to 64 := 0
adj_time7i  integer range 0 to 64 := 0
adj_time0_i  integer range 0 to 32 := 0
adj_time1_i  integer range 0 to 32 := 0
adj_time2_i  integer range 0 to 32 := 0
adj_time3_i  integer range 0 to 32 := 0
adj_time4_i  integer range 0 to 32 := 0
adj_time5_i  integer range 0 to 32 := 0
adj_time6_i  integer range 0 to 32 := 0
adj_time7_i  integer range 0 to 32 := 0
adj_time02_i  integer range 0 to 32 := 0
adj_time12_i  integer range 0 to 32 := 0
adj_time22_i  integer range 0 to 32 := 0
adj_time32_i  integer range 0 to 32 := 0
adj_time42_i  integer range 0 to 32 := 0
adj_time52_i  integer range 0 to 32 := 0
adj_time62_i  integer range 0 to 32 := 0
adj_time72_i  integer range 0 to 32 := 0
control2_i  std_logic_vector ( 35 downto 0 )
 signals for Chipscope Cores
control1_i  std_logic_vector ( 35 downto 0 )
 signals for Chipscope Cores
control0_i  std_logic_vector ( 35 downto 0 )
 signals for Chipscope Cores
probe3_i  std_logic_vector ( 49 downto 0 )
probe2_i  std_logic_vector ( 49 downto 0 )
probe1_i  std_logic_vector ( 49 downto 0 )
pktcnt  std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
pktcnt2  std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
pktcnt3  std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
pktcnt4  std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
pktcnt5  std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
ctor_debug  std_logic_vector ( 22 downto 0 ) := ( others = > ' 0 ' )

Attributes

fsm_encoding  string
 configs for timewindows
fsm_encoding  " gray "
safe_implementation  string
 force FSM safety logic implementation
safe_implementation  " yes "

Component Instantiations

daq rios_all <Entity rios_all>
edge_fal_det edge_fal <Entity edge_fal>
raw_data_gen raw_data_emul <Entity raw_data_emul>
proc_data_gen proc_data_emul <Entity proc_data_emul>
algo_a delta_t_ac_top <Entity delta_t_ac_top>
 Algo A: 1-to-1 coincidence between side A & C within time window.
algo_b delta_t_ac_top <Entity delta_t_ac_top>
 Algo B: 2-to-2 coincidence between side A & C within time window.
algo_c delta_t_ac_top <Entity delta_t_ac_top>
 Algo C: One hit within time window.
algo_d delta_t_ac_top <Entity delta_t_ac_top>
 Algo D: Two hits within time window.
intime_cuts intime <Entity intime>
mem_reset_extend extend_test <Entity extend_test>
complete_extend extend_test <Entity extend_test>
proc_buffer ddr_data_buffer <Entity ddr_data_buffer>
proc_memory ram_user_backend <Entity ram_user_backend>
countddrreads cnt_ddr_rd <Entity cnt_ddr_rd>
ddreth_buf ddr_eth_buf <Entity ddr_eth_buf>
ddr_udp_chksum_1 ddr_chksum_cal <Entity ddr_chksum_cal>
ddr_clr_extend extend_test <Entity extend_test>
IOBUF_inst IOBUF
 no DDR RAM
IOBUF_inst2 IOBUF
 Bidirectional buffer.
OBUF_inst OBUF
 Output buffer.
OBUF_inst2 OBUF
 Output buffer.
OBUF_inst3 OBUF
 Output buffer.
OBUF_inst4 OBUF
 Output buffer.
OBUF_inst5 OBUF
 Output buffer.
OBUF_inst6 OBUF
 Output buffer.
OBUF_inst7 OBUF
 Output buffer.
OBUF_inst8 OBUF
 Output buffer.
OBUF_inst9 OBUF
 Output buffer.
OBUF_inst10 OBUF
 Output buffer.
raw_buffer ddr2_data_buffer <Entity ddr2_data_buffer>
 buffer 200 MHz for DDR2
raw_memory ddr2_usr_be <Entity ddr2_usr_be>
countddr2reads cnt_ddr2_rd <Entity cnt_ddr2_rd>
ddr2_eth_buf eth_buf <Entity eth_buf>
ddr2_udp_chksum_1 ddr2_chksum_cal <Entity ddr2_chksum_cal>
ddr2_clr_extend extend_test <Entity extend_test>
clk_hz_sync edge <Entity edge>
start_extend extend_test <Entity extend_test>
pktdone_extend extend_test <Entity extend_test>
 extend pktdone
eth ethernet_top <Entity ethernet_top>
rd_rdy_sync edge <Entity edge>
READ_OVER_extend extend_test <Entity extend_test>
rd_ovr_sync edge <Entity edge>
PC_decoder command_decoder <Entity command_decoder>
 decode commands from PC
sl_end_force_extend extend_test <Entity extend_test>
l1a_force_extend extend_test <Entity extend_test>
l1a_force_sync edge <Entity edge>
ackw_extend extend_test <Entity extend_test>
acka_extend extend_test <Entity extend_test>
acki_extend extend_test <Entity extend_test>
ackb_extend extend_test <Entity extend_test>
start_run_extend extend_test <Entity extend_test>
start_run_sync edge <Entity edge>
reset_extend extend_test <Entity extend_test>
rate_reset_extend extend_test <Entity extend_test>
rio_reset_extend extend_test <Entity extend_test>
dcs_bufr BUFR
 DCS collector clock.
dcs_msg_ctor status_collector <Entity status_collector>
TDAQ_LVL1_buf lvl1_buf <Entity lvl1_buf>
L1A_delay bcm_signal_delay <Entity bcm_signal_delay>
latency_bcr_delay bcm_signal_delay <Entity bcm_signal_delay>
l1a_sync edge <Entity edge>
bunch_counter BID_cnt <Entity BID_cnt>
Level_1_trigger_fifo l1a_fifo <Entity l1a_fifo>
rod_command_extend1 extend_test <Entity extend_test>
rod_command_sync1 edge <Entity edge>
rod_command_extend2 extend_test <Entity extend_test>
rod_command_sync2 edge <Entity edge>
busy_extend extend_test <Entity extend_test>
rod bcm_rod <Entity bcm_rod>
tdaq_msg_ctor tdaq_collector <Entity tdaq_collector>
command_extend11 extend_test <Entity extend_test>
command_extend_ecr extend_test <Entity extend_test>
 extend l1a_load
command_extend21 extend_test <Entity extend_test>
command_extend_orb extend_test <Entity extend_test>
 extend l1a_load
command_extend12 extend_test <Entity extend_test>
command_extend_bcr_force extend_test <Entity extend_test>
 extend bcr force
command_extend_ecr_force extend_test <Entity extend_test>
 extend ecr force
Orbit_delay bcm_signal_delay <Entity bcm_signal_delay>
ltp_rcd ltp_comm <Entity ltp_comm>
command_extend6 extend_test <Entity extend_test>
command_extend7 extend_test <Entity extend_test>
command_extend8 extend_test <Entity extend_test>
command_extend9 extend_test <Entity extend_test>
DSS dss_comm <Entity dss_comm>
ctplogic ctp_logic <Entity ctp_logic>
command_extend1 extend_test <Entity extend_test>
 Time win upper side A, A to C.
CTP_intf ctp_comm <Entity ctp_comm>
command_extend2 extend_test <Entity extend_test>
command_extend3 extend_test <Entity extend_test>
CIBU cibu_comm <Entity cibu_comm>
abort_contr abort_controller <Entity abort_controller>
 internal beam abort logic
sata_wrapper bridge <Entity bridge>
chipscope_cntr icon <Entity icon>
 Chipscope.
chipscope_probe1 ila
chipscope_probe2 ila
chipscope_probe3 ila

Detailed Description

Contains all major design modules (RAMs, RIO, EMAC).

In this Entity all major design parts are contained: both of the two big RAMs with their support logic & interface buffers, the EMAC for Ethernet connectability, the DAQ-RocketIOs, the ROD part with the SLINK interface & the time-window-coincidence logic module. Furthermore a FSM controlling the sequential read-out of the two big memories is also in here.

Definition at line 198 of file rio2mem.vhd.

Member Function Documentation

[Process]
ackvld_rsff ( EMAC_CLK )

set/reset ack_vld signal

Definition at line 2416 of file rio2mem.vhd.

02416   ackvld_rsff : process (EMAC_CLK)
02417   begin  -- process ackvld_rsff
02418     if EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
02419       if RESET = '1' then
02420         ack_vld_ff <= '0';
02421       else
02422         if start_pkt = '1' then
02423           ack_vld_ff <= '0';
02424         elsif ack_vld = '1' then
02425           ack_vld_ff <= '1';
02426         end if;
02427       end if;
02428     end if;
02429   end process ackvld_rsff;

[Process]
busy_ext_latch ( EMAC_CLK ,
RESET )

latch busy from TDAQ software

Definition at line 2726 of file rio2mem.vhd.

02726   busy_ext_latch : process (EMAC_CLK, RESET)
02727   begin  -- process busy_ext_latch
02728     if EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
02729       if RESET = '1' then               -- synchronous reset (active high)
02730         busy_ext <= '1';
02731       else
02732         if busy_clr = '1' then
02733           busy_ext <= '0';
02734         elsif busy_ext_rs = '1' then
02735           busy_ext <= '1';
02736         end if;
02737       end if;
02738     end if;
02739   end process busy_ext_latch;

[Process]
count_backa ( BCLK )

count out-of-time coincidences A

Definition at line 1488 of file rio2mem.vhd.

01488   count_backa : process (BCLK)
01489   begin  -- process count_backa
01490     if BCLK'event and BCLK = '1' then   -- rising clock edge
01491       if (RESET or rate_reset_i or rate_block) = '1' then
01492         cnt_backa <= (others => '0');
01493       elsif delta_vld_backa = '1' then
01494         cnt_backa <= cnt_backa + 1;
01495       else
01496         cnt_backa <= cnt_backa;
01497       end if;
01498     end if;
01499   end process count_backa;

[Process]
count_backc ( BCLK )

count out-of-time coincidences C

Definition at line 1502 of file rio2mem.vhd.

01502   count_backc : process (BCLK)
01503   begin  -- process count_backc
01504     if BCLK'event and BCLK = '1' then   -- rising clock edge
01505       if (RESET or rate_reset_i or rate_block) = '1' then
01506         cnt_backc <= (others => '0');
01507       elsif delta_vld_backc = '1' then
01508         cnt_backc <= cnt_backc + 1;
01509       else
01510         cnt_backc <= cnt_backc;
01511       end if;
01512     end if;
01513   end process count_backc;

[Process]
count_ch1 ( BCLK )

count hits ch1

Definition at line 1516 of file rio2mem.vhd.

01516   count_ch1 : process (BCLK)
01517   begin
01518     if BCLK'event and BCLK = '1' then   -- rising clock edge
01519       if (RESET or rate_reset_i or rate_block or rio_trip(0)) = '1' then
01520         cnt_ch1 <= (others => '0');
01521       else
01522         if input_en_status(0) = '1' then
01523           cnt_ch1 <= cnt_ch1 + proc_data_ii(191) + proc_data_ii(179);
01524         end if;
01525       end if;
01526     end if;
01527   end process count_ch1;

[Process]
count_ch2 ( BCLK )

count hits ch2

Definition at line 1530 of file rio2mem.vhd.

01530   count_ch2 : process (BCLK)
01531   begin
01532     if BCLK'event and BCLK = '1' then   -- rising clock edge
01533       if (RESET or rate_reset_i or rate_block or rio_trip(1)) = '1' then
01534         cnt_ch2 <= (others => '0');
01535       else
01536         if input_en_status(1) = '1' then
01537           cnt_ch2 <= cnt_ch2 + proc_data_ii(167) + proc_data_ii(155);
01538         end if;
01539       end if;
01540     end if;
01541   end process count_ch2;

[Process]
count_ch3 ( BCLK )

count hits ch3

Definition at line 1544 of file rio2mem.vhd.

01544   count_ch3 : process (BCLK)
01545   begin
01546     if BCLK'event and BCLK = '1' then   -- rising clock edge
01547       if (RESET or rate_reset_i or rate_block or rio_trip(2)) = '1' then
01548         cnt_ch3 <= (others => '0');
01549       else
01550         if input_en_status(2) = '1' then
01551           cnt_ch3 <= cnt_ch3 + proc_data_ii(143) + proc_data_ii(131);
01552         end if;
01553       end if;
01554     end if;
01555   end process count_ch3;

[Process]
count_ch4 ( BCLK )

count hits ch4

Definition at line 1558 of file rio2mem.vhd.

01558   count_ch4 : process (BCLK)
01559   begin
01560     if BCLK'event and BCLK = '1' then   -- rising clock edge
01561       if (RESET or rate_reset_i or rate_block or rio_trip(3)) = '1' then
01562         cnt_ch4 <= (others => '0');
01563       else
01564         if input_en_status(3) = '1' then
01565           cnt_ch4 <= cnt_ch4 + proc_data_ii(119) + proc_data_ii(107);
01566         end if;
01567       end if;
01568     end if;
01569   end process count_ch4;

[Process]
count_ch5 ( BCLK )

count hits ch5

Definition at line 1572 of file rio2mem.vhd.

01572   count_ch5 : process (BCLK)
01573   begin
01574     if BCLK'event and BCLK = '1' then   -- rising clock edge
01575       if (RESET or rate_reset_i or rate_block or rio_trip(4)) = '1' then
01576         cnt_ch5 <= (others => '0');
01577       else
01578         if input_en_status(4) = '1' then
01579           cnt_ch5 <= cnt_ch5 + proc_data_ii(95) + proc_data_ii(83);
01580         end if;
01581       end if;
01582     end if;
01583   end process count_ch5;

[Process]
count_ch6 ( BCLK )

count hits ch6

Definition at line 1586 of file rio2mem.vhd.

01586   count_ch6 : process (BCLK)
01587   begin
01588     if BCLK'event and BCLK = '1' then   -- rising clock edge
01589       if (RESET or rate_reset_i or rate_block or rio_trip(5)) = '1' then
01590         cnt_ch6 <= (others => '0');
01591       else
01592         if input_en_status(5) = '1' then
01593           cnt_ch6 <= cnt_ch6 + proc_data_ii(71) + proc_data_ii(59);
01594         end if;
01595       end if;
01596     end if;
01597   end process count_ch6;

[Process]
count_ch7 ( BCLK )

count hits ch7

Definition at line 1600 of file rio2mem.vhd.

01600   count_ch7 : process (BCLK)
01601   begin
01602     if BCLK'event and BCLK = '1' then   -- rising clock edge
01603       if (RESET or rate_reset_i or rate_block or rio_trip(6)) = '1' then
01604         cnt_ch7 <= (others => '0');
01605       else
01606         if input_en_status(6) = '1' then
01607           cnt_ch7 <= cnt_ch7 + proc_data_ii(47) + proc_data_ii(35);
01608         end if;
01609       end if;
01610     end if;
01611   end process count_ch7;

[Process]
count_ch8 ( BCLK )

count hits ch8

Definition at line 1614 of file rio2mem.vhd.

01614   count_ch8 : process (BCLK)
01615   begin
01616     if BCLK'event and BCLK = '1' then   -- rising clock edge
01617       if (RESET or rate_reset_i or rate_block or rio_trip(7)) = '1' then
01618         cnt_ch8 <= (others => '0');
01619       else
01620         if input_en_status(7) = '1' then
01621           cnt_ch8 <= cnt_ch8 + proc_data_ii(23) + proc_data_ii(11);
01622         end if;
01623       end if;
01624     end if;
01625   end process count_ch8;

[Process]
count_coins ( BCLK )

count in-time coincidences

Definition at line 1474 of file rio2mem.vhd.

01474   count_coins : process (BCLK)
01475   begin  -- process count_coins
01476     if BCLK'event and BCLK = '1' then   -- rising clock edge
01477       if (RESET or rate_reset_i or rate_block) = '1' then
01478         cnt_coin <= (others => '0');
01479       elsif delta_vld_a = '1' then
01480         cnt_coin <= cnt_coin + 1;
01481       else
01482         cnt_coin <= cnt_coin;
01483       end if;
01484     end if;
01485   end process count_coins;

[Process]
emac_manager ( EMAC_CLK ,
RESET )

FSM to manage access to EMAC.

Definition at line 2242 of file rio2mem.vhd.

02242   emac_manager : process (EMAC_CLK, RESET)
02243   begin  -- process emac_manager
02244     if RESET = '1' then                 -- asynchronous reset (active high)
02245       ems             <= e_idle;
02246       en_mem          <= '0';
02247       en_stat_mac_set <= '0';
02248       assemb_stat     <= '0';
02249       en_tdaq_mac_set <= '0';
02250       assemb_tdaq     <= '0';
02251       start_nxt_st    <= '0';
02252     elsif EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
02253       en_mem          <= '0';
02254       en_stat_mac_set <= '0';
02255       assemb_stat     <= '0';
02256       en_tdaq_mac_set <= '0';
02257       assemb_tdaq     <= '0';
02258       start_nxt_st    <= '0';
02259 
02260       case ems is
02261         
02262         when e_idle =>
02263           if second_active = '1' then
02264             ems <= e_fillstat;
02265           elsif tdaq_active = '1' then
02266             ems <= e_filltdaq;
02267           elsif read_out_i = '1' then
02268             ems <= e_dump;
02269           end if;
02270 
02271         when e_dump =>
02272           en_mem <= '1';
02273           if (second_active and pktdone_ff) = '1' then
02274             ems <= e_fillstat;
02275           elsif (tdaq_active and pktdone_ff) = '1' then
02276             ems <= e_filltdaq;
02277           end if;
02278 
02279         when e_fillstat =>
02280           assemb_stat <= '1';
02281           if stat_asm_done_i = '1' then
02282             assemb_stat     <= '0';
02283             en_stat_mac_set <= '1';
02284             ems             <= e_stat;
02285           end if;
02286 
02287         when e_stat =>
02288           if stat_msg_done = '1' then
02289             if read_out_i = '1' then
02290               ems          <= e_dump;
02291               start_nxt_st <= '1';
02292             else
02293               ems <= e_idle;
02294             end if;
02295           else
02296             ems <= e_stat;
02297           end if;
02298 
02299         when e_filltdaq =>
02300           assemb_tdaq <= '1';
02301           if tdaq_asm_done_i = '1' then
02302             assemb_tdaq     <= '0';
02303             en_tdaq_mac_set <= '1';
02304             ems             <= e_tdaq;
02305           end if;
02306 
02307         when e_tdaq =>
02308           if tdaq_msg_done = '1' then
02309             if read_out_i = '1' then
02310               ems          <= e_dump;
02311               start_nxt_st <= '1';
02312             else
02313               ems <= e_idle;
02314             end if;
02315           else
02316             ems <= e_tdaq;
02317           end if;
02318           
02319         when others => null;
02320       end case;
02321     end if;
02322   end process emac_manager;

[Process]
empty_flag ( BCLK ,
lvl1_buf_res )

empty flag of L1A-FIFO

Definition at line 3315 of file rio2mem.vhd.

03315   empty_flag : process (BCLK, lvl1_buf_res)
03316   begin  -- process empty_flag
03317     if lvl1_buf_res = '1' then            -- asynchronous reset (active high)
03318       l1a_fifo_fill <= (others => '0');
03319       lf_empty      <= '1';
03320       lf_full       <= '0';
03321     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
03322       if (lf_wren and lf_rden) = '1' then
03323         l1a_fifo_fill <= l1a_fifo_fill;
03324       elsif (lf_wren = '1' and l1a_fifo_fill /= 31) then
03325         l1a_fifo_fill <= l1a_fifo_fill + 1;
03326       elsif (lf_rden = '1' and l1a_fifo_fill /= 0) then
03327         l1a_fifo_fill <= l1a_fifo_fill - 1;
03328       end if;
03329       if (l1a_fifo_fill = 0 and lf_full = '0') then
03330         lf_empty <= '1';
03331       else
03332         lf_empty <= '0';
03333       end if;
03334       if lf_empty = '1' then
03335         lf_full <= '0';
03336       elsif l1a_fifo_fill >= 29 then
03337         lf_full <= '1';
03338       else
03339         lf_full <= '0';
03340       end if;
03341     end if;
03342   end process empty_flag;

[Process]
en_arp ( EMAC_CLK ,
RESET )

ARP announcement after reboot.

Definition at line 2581 of file rio2mem.vhd.

02581   en_arp : process(EMAC_CLK, RESET)
02582     variable cnt : integer range 0 to 31 := 0;
02583   begin
02584     if EMAC_CLK'event and EMAC_CLK = '1' then
02585       if RESET = '1' then
02586         cnt      := 0;
02587         arp_i    <= '0';
02588         arp_done <= '0';
02589       else
02590         if arp_ii = '1' then
02591           if cnt > 15 then
02592             cnt := cnt;
02593           else
02594             cnt := cnt + 1;
02595           end if;
02596           if cnt <= 15 and cnt > 5 then
02597             arp_i <= '1';
02598           else
02599             arp_i <= '0';
02600           end if;
02601         else
02602           arp_i <= '0';
02603         end if;
02604         if cnt > 5 then
02605           arp_done <= '1';
02606         end if;
02607       end if;
02608     end if;
02609   end process en_arp;

[Process]
l1a_fifo_buffer_interface ( BCLK ,
RESET )

interface logic between L1A fifo and Level-1 data buffer

Definition at line 3393 of file rio2mem.vhd.

03393   l1a_fifo_buffer_interface : process (BCLK, RESET)
03394     variable cs, ds : std_logic_vector(1 downto 0) := "00";
03395     variable push   : integer                      := 0;
03396   begin  -- process l1a_fifo_buffer_interface
03397     if RESET = '1' then                   -- asynchronous reset (active high)
03398       cs      := "00";
03399       lf_rden <= '0';
03400       push    := 0;
03401     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
03402       cs      := ds;
03403       lf_rden <= '0';
03404       case cs is
03405         when "00" =>
03406           if lf_empty = '0' and busy_i = '0' then
03407             lf_rden <= '1';
03408             ds      := "01";
03409             push    := 0;
03410           end if;
03411         when "01" =>
03412           if (next_l1a = '1') and (push = 5) then
03413             ds := "00";
03414           end if;
03415           if push = 5 then
03416             push := push;
03417           else
03418             push := push+1;
03419           end if;
03420         when others => null;
03421       end case;
03422     end if;
03423   end process l1a_fifo_buffer_interface;

[Process]
l1adone_latch ( BCLK ,
RESET )

wait with next l1a until rod formatter is ready

Definition at line 3354 of file rio2mem.vhd.

03354   l1adone_latch : process (BCLK, RESET)
03355   begin  -- process donelatch
03356     if RESET = '1' then                   -- asynchronous reset (active high)
03357       next_l1a <= '1';
03358     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
03359       if lf_rden = '1' then
03360         next_l1a <= '0';
03361       elsif get_next_l1a = '1' then
03362         next_l1a <= '1';
03363       end if;
03364     end if;
03365   end process l1adone_latch;

[Process]
l1adone_latch1 ( BCLK ,
RESET )

wait with next l1a until rod formatter is ready, signaling end of last burst

Definition at line 3368 of file rio2mem.vhd.

03368   l1adone_latch1 : process (BCLK, RESET)
03369   begin  -- process donelatch
03370     if RESET = '1' then                   -- asynchronous reset (active high)
03371       next_l1a1 <= '0';
03372     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
03373       if l1a_done = '1' then
03374         next_l1a1 <= '1';
03375       elsif busy_i = '0' then
03376         next_l1a1 <= '0';
03377       end if;
03378     end if;
03379   end process l1adone_latch1;

[Process]
nllatches ( BCLK )

get falling edge

Definition at line 3382 of file rio2mem.vhd.

03382   nllatches : process(BCLK)
03383   begin
03384     if BCLK'event and BCLK = '1' then
03385       nllatch1 <= next_l1a1;
03386       nllatch2 <= nllatch1;
03387     end if;
03388   end process nllatches;

[Process]
overflow_flag_proc ( BCLK4X_P ,
mem_reset )

produce buffer overflow flag

Definition at line 1873 of file rio2mem.vhd.

01873     overflow_flag_proc : process (BCLK4X_P, mem_reset)
01874     begin  -- process overflow_flag_raw
01875       if mem_reset = '1' then           -- asynchronous reset (active high)
01876         over_proc_i <= '0';
01877       elsif BCLK4X_P'event and BCLK4X_P = '1' then  -- rising clock edge
01878         if rw_proc_i = '0' and proc_trans_complete = '1' then
01879           over_proc_i <= '1';
01880         end if;
01881       end if;
01882     end process overflow_flag_proc;

[Process]
overflow_flag_raw ( REFCLK_P ,
mem_reset )

produce buffer overflow flag

Definition at line 2135 of file rio2mem.vhd.

02135   overflow_flag_raw : process (REFCLK_P, mem_reset)
02136   begin  -- process overflow_flag_raw
02137     if mem_reset = '1' then             -- asynchronous reset (active high)
02138       over_raw_i <= '0';
02139     elsif REFCLK_P'event and REFCLK_P = '1' then  -- rising clock edge
02140       if rw_raw_i = '0' and raw_trans_complete = '1' then
02141         over_raw_i <= '1';
02142       end if;
02143     end if;
02144   end process overflow_flag_raw;

[Process]
pktdone_rsff ( EMAC_CLK )

set/reset pktdone signal

Definition at line 2400 of file rio2mem.vhd.

02400   pktdone_rsff : process (EMAC_CLK)
02401   begin  -- process pktdone_rsff
02402     if EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
02403       if RESET = '1' then
02404         pktdone_ff <= '0';
02405       else
02406         if (assemb_tdaq or assemb_stat) = '1' then
02407           pktdone_ff <= '0';
02408         elsif pktdone = '1' then
02409           pktdone_ff <= '1';
02410         end if;
02411       end if;
02412     end if;
02413   end process pktdone_rsff;

[Process]
readout_controller_fsm ( REFCLK_P )

readout control FSM

Definition at line 1691 of file rio2mem.vhd.

01691   readout_controller_fsm : process(REFCLK_P)
01692   begin
01693     if REFCLK_P'event and REFCLK_P = '1' then
01694       if RESET = '1' then
01695         cs          <= r_idle;
01696         start_rdout <= '0';
01697       else
01698         case cs is
01699           when r_idle =>
01700             if read_out_i = '1' then
01701               if kUseDDR = true then
01702                 cs <= r_proc;
01703               else
01704                 cs <= r_raw;
01705               end if;
01706               start_rdout <= '1';
01707             else
01708               cs          <= r_idle;
01709               start_rdout <= '0';
01710             end if;
01711           when r_proc =>
01712             if swtoerr_ff = '1' then
01713               cs <= r_err;
01714             else
01715               start_rdout <= '0';
01716               if proc_trans_complete = '1' then
01717                 cs <= r_raw;
01718               else
01719                 cs <= r_proc;
01720               end if;
01721             end if;
01722           when r_raw =>
01723             if swtoerr_ff = '1' then
01724               cs <= r_err;
01725             else
01726               start_rdout <= '0';
01727               if raw_trans_complete = '1' then
01728                 cs <= r_idle;
01729               else
01730                 cs <= r_raw;
01731               end if;
01732             end if;
01733           when r_err =>
01734             if err_msg_complete = '1' then
01735               cs <= r_idle;
01736             else
01737               cs <= r_err;
01738             end if;
01739           when others =>
01740             start_rdout <= '0';
01741             cs          <= r_err;
01742         end case;
01743       end if;
01744     end if;
01745   end process readout_controller_fsm;

[Process]
readout_controller_proc ( BCLK4X_P )

DDR RAM.

control FSM for DDR

Definition at line 1773 of file rio2mem.vhd.

01773     readout_controller_proc : process(BCLK4X_P)
01774       variable cnt_br_proc : integer range 0 to 31 := 0;
01775     begin
01776       if BCLK4X_P'event and BCLK4X_P = '1' then
01777         if mem_reset = '1' then
01778           en_rd_proc      <= '0';
01779           cnt_br_proc     := 0;
01780           pkt_rddone_proc <= '0';
01781         else
01782           pkt_rddone_proc <= '0';
01783           if cs = r_proc and en_mem = '1' then
01784             if start_pkt = '1' then
01785               cnt_br_proc := 0;
01786             elsif cnt_br_proc < 21 then
01787 --* count "empty" bursts, we need 6 rd-bursts, 1 burst = 4 clk cycles => cnt_br
01788 --* = 21 during first cycle of 6 empty burst
01789               if burstind_proc = '1' then
01790                 cnt_br_proc := cnt_br_proc + 1;
01791               else
01792                 cnt_br_proc := cnt_br_proc;
01793               end if;
01794               en_rd_proc <= '1';
01795             else
01796               if cnt_br_proc = 21 then
01797                 pkt_rddone_proc <= '1';
01798                 cnt_br_proc     := cnt_br_proc + 1;
01799               else
01800                 cnt_br_proc := cnt_br_proc;
01801                 en_rd_proc  <= '0';
01802               end if;
01803             end if;
01804           else
01805             cnt_br_proc := 0;
01806             en_rd_proc  <= '0';
01807           end if;
01808         end if;
01809       end if;
01810     end process readout_controller_proc;

[Process]
readout_controller_raw ( REFCLK_P )

control FSM for DDR2

Definition at line 2031 of file rio2mem.vhd.

02031   readout_controller_raw : process(REFCLK_P)
02032     variable cnt_br_raw : integer range 0 to 15 := 0;
02033   begin
02034     if REFCLK_P'event and REFCLK_P = '1' then
02035       if mem_reset = '1' then
02036         en_rd_raw      <= '0';
02037         cnt_br_raw     := 0;
02038         pkt_rddone_raw <= '0';
02039       else
02040         pkt_rddone_raw <= '0';
02041         if cs = r_raw and en_mem = '1' then
02042           if start_pkt = '1' then
02043             cnt_br_raw := 0;
02044           elsif cnt_br_raw < 9 then
02045             if burstind_raw = '1' then
02046 --* count "empty" bursts, we need 3 rd-bursts, 1 burst = 4 clk cycles => cnt_br
02047 --* = 9 during first cycle of 3 empty burst
02048               cnt_br_raw := cnt_br_raw + 1;
02049             else
02050               cnt_br_raw := cnt_br_raw;
02051             end if;
02052             en_rd_raw <= '1';
02053           else
02054             if cnt_br_raw = 9 then
02055               pkt_rddone_raw <= '1';
02056               cnt_br_raw     := cnt_br_raw + 1;
02057             else
02058               cnt_br_raw := cnt_br_raw;
02059               en_rd_raw  <= '0';
02060             end if;
02061           end if;
02062         end if;
02063       end if;
02064     end if;
02065   end process readout_controller_raw;

[Process]
set_second_active ( EMAC_CLK ,
RESET )

register 1Hz frequency

Definition at line 2206 of file rio2mem.vhd.

02206   set_second_active : process (EMAC_CLK, RESET)
02207   begin  -- process set_second_active
02208     if EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
02209       if RESET = '1' then
02210         second_active <= '0';
02211       else
02212         if arp_done = '1' then          --* start only after arp ann is done
02213           if stat_msg_done = '1' then
02214             second_active <= '0';
02215           elsif (second or get_stats) = '1' then
02216             second_active <= '1';
02217           end if;
02218         end if;
02219       end if;
02220     end if;
02221   end process set_second_active;

[Process]
set_tdaq_active ( EMAC_CLK ,
RESET )

register TDAQ status request

Definition at line 2224 of file rio2mem.vhd.

02224   set_tdaq_active : process (EMAC_CLK, RESET)
02225   begin  -- process set_second_active
02226     if EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
02227       if RESET = '1' then
02228         tdaq_active <= '0';
02229       else
02230         if arp_done = '1' then          --* start only after arp ann is done
02231           if tdaq_msg_done = '1' then
02232             tdaq_active <= '0';
02233           elsif send_tdaq_status = '1' then
02234             tdaq_active <= '1';
02235           end if;
02236         end if;
02237       end if;
02238     end if;
02239   end process set_tdaq_active;

[Process]
shift_clear_ddr ( BCLK4X_P )

shift mem_reset by 5 clk cycles to start clear of eth buffers

Definition at line 1756 of file rio2mem.vhd.

01756   shift_clear_ddr : process(BCLK4X_P)
01757   begin
01758     if BCLK4X_P'event and BCLK4X_P = '1' then
01759       clr_ddr   <= clr_shift(4);
01760       clr_shift <= clr_shift(3 downto 0) & mem_reset;
01761     end if;
01762   end process shift_clear_ddr;

[Process]
shift_clear_ddr2 ( REFCLK_P )

shift mem_reset by 5 clk cycles to start clear of eth buffers

Definition at line 1748 of file rio2mem.vhd.

01748   shift_clear_ddr2 : process(REFCLK_P)
01749   begin
01750     if REFCLK_P'event and REFCLK_P = '1' then
01751       clr_ddr2   <= clr_shift2(4);
01752       clr_shift2 <= clr_shift2(3 downto 0) & mem_reset;
01753     end if;
01754   end process shift_clear_ddr2;

[Process]
start ( CLK_HZ ,
RESET )

ARP announcement after reboot.

Definition at line 2558 of file rio2mem.vhd.

02558   start : process(CLK_HZ, RESET)
02559     variable cnt : integer range 0 to 7 := 0;
02560   begin
02561     if RESET = '1' then
02562       cnt    := 0;
02563       arp_ii <= '0';
02564     elsif CLK_HZ'event and CLK_HZ = '1' then
02565       if mac_lock_i = '1' then
02566         if cnt > 5 then
02567           cnt := cnt;
02568         else
02569           cnt := cnt + 1;
02570         end if;
02571         if cnt = 5 then
02572           arp_ii <= '1';
02573         else
02574           arp_ii <= '0';
02575         end if;
02576       end if;
02577     end if;
02578   end process start;

[Process]
start_pkt_rsff ( EMAC_CLK )

set/reset start_pkt signal

Definition at line 2435 of file rio2mem.vhd.

02435   start_pkt_rsff : process (EMAC_CLK)
02436   begin  -- process start_pkt_rsff
02437     if EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
02438       if RESET = '1' then
02439         start_pkt_ff <= '0';
02440       else
02441         if pktdone = '1' then
02442           start_pkt_ff <= '0';
02443         elsif start_pkt = '1' then
02444           start_pkt_ff <= '1';
02445         end if;
02446       end if;
02447     end if;
02448   end process start_pkt_rsff;

[Process]
stat_pkt_rsff ( EMAC_CLK )

set/reset stat_pkt signal

Definition at line 2451 of file rio2mem.vhd.

02451   stat_pkt_rsff : process (EMAC_CLK)
02452   begin  -- process stat_pkt_rsff
02453     if EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
02454       if RESET = '1' then
02455         en_stat_mac <= '0';
02456       else
02457         if stat_msg_rd_done = '1' then
02458           en_stat_mac <= '0';
02459         elsif en_stat_mac_set = '1' then
02460           en_stat_mac <= '1';
02461         end if;
02462       end if;
02463     end if;
02464   end process stat_pkt_rsff;

[Process]
sw_to_err ( REFCLK_P ,
RESET )

switch to sending of error message

purpose: switch to error_state only after finishing pkt
type : sequential
inputs : REFCLK_P, RESET, SEND_ERR_MSG, pktdone
outputs: swtoerr_i

Definition at line 1674 of file rio2mem.vhd.

01674   sw_to_err : process (REFCLK_P, RESET)
01675   begin  -- process sw_to_err
01676     if RESET = '1' then                 -- asynchronous reset (active high)
01677       swtoerr_ff <= '0';
01678     elsif REFCLK_P'event and REFCLK_P = '1' then  -- rising clock edge
01679       if SEND_ERR_MSG = '1' then
01680         swtoerr_ff <= '1';
01681       else
01682         swtoerr_ff <= '0';
01683       end if;
01684       if pktdone = '1' then
01685         swtoerr_ff <= '0';
01686       end if;
01687     end if;
01688   end process sw_to_err;

[Process]
tdaq_pkt_rsff ( EMAC_CLK )

set/reset tdaq_pkt signal

Definition at line 2467 of file rio2mem.vhd.

02467   tdaq_pkt_rsff : process (EMAC_CLK)
02468   begin  -- process stat_pkt_rsff
02469     if EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
02470       if RESET = '1' then
02471         en_tdaq_mac <= '0';
02472       else
02473         if tdaq_msg_rd_done = '1' then
02474           en_tdaq_mac <= '0';
02475         elsif en_tdaq_mac_set = '1' then
02476           en_tdaq_mac <= '1';
02477         end if;
02478       end if;
02479     end if;
02480   end process tdaq_pkt_rsff;

[Process]
toggle_data_generation ( EMAC_CLK ,
RESET )

switch internal data generation on and off

Definition at line 2742 of file rio2mem.vhd.

02742   toggle_data_generation : process (EMAC_CLK, RESET)
02743   begin  -- process
02744     if EMAC_CLK'event and EMAC_CLK = '1' then
02745       if RESET = '1' then
02746         pat_fill <= '0';
02747       else
02748         if fill_buf_i = '1' then
02749           pat_fill <= not pat_fill;
02750         end if;
02751       end if;
02752     end if;
02753   end process;

[Process]
trigger_rate_1 ( BCLK ,
RESET )

trigger rates

Definition at line 3990 of file rio2mem.vhd.

03990   trigger_rate_1 : process (BCLK, RESET)
03991   begin  -- process trigger_rate_1
03992     if RESET = '1' then                   -- asynchronous reset (active high)
03993       trig_rate_AttC <= (others => '0');
03994     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
03995       if ctp_int(9) = '1' then
03996         trig_rate_AttC <= trig_rate_AttC + 1;
03997       end if;
03998     end if;
03999   end process trigger_rate_1;

[Process]
trigger_rate_2 ( BCLK ,
RESET )

trigger rates

Definition at line 4002 of file rio2mem.vhd.

04002   trigger_rate_2 : process (BCLK, RESET)
04003   begin  -- process trigger_rate_1
04004     if RESET = '1' then                   -- asynchronous reset (active high)
04005       trig_rate_AttA <= (others => '0');
04006     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04007       if ctp_int(8) = '1' then
04008         trig_rate_AttA <= trig_rate_AttA + 1;
04009       end if;
04010     end if;
04011   end process trigger_rate_2;

[Process]
trigger_rate_3 ( BCLK ,
RESET )

trigger rates

Definition at line 4014 of file rio2mem.vhd.

04014   trigger_rate_3 : process (BCLK, RESET)
04015   begin  -- process trigger_rate_1
04016     if RESET = '1' then                   -- asynchronous reset (active high)
04017       trig_rate_Wide <= (others => '0');
04018     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04019       if ctp_int(3) = '1' then
04020         trig_rate_Wide <= trig_rate_Wide + 1;
04021       end if;
04022     end if;
04023   end process trigger_rate_3;

[Process]
trigger_rate_4 ( BCLK ,
RESET )

trigger rates

Definition at line 4026 of file rio2mem.vhd.

04026   trigger_rate_4 : process (BCLK, RESET)
04027   begin  -- process trigger_rate_1
04028     if RESET = '1' then                   -- asynchronous reset (active high)
04029       trig_rate_CtoA <= (others => '0');
04030     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04031       if ctp_int(2) = '1' then
04032         trig_rate_CtoA <= trig_rate_CtoA + 1;
04033       end if;
04034     end if;
04035   end process trigger_rate_4;

[Process]
trigger_rate_5 ( BCLK ,
RESET )

trigger rates

Definition at line 4038 of file rio2mem.vhd.

04038   trigger_rate_5 : process (BCLK, RESET)
04039   begin  -- process trigger_rate_1
04040     if RESET = '1' then                   -- asynchronous reset (active high)
04041       trig_rate_AtoC <= (others => '0');
04042     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04043       if ctp_int(1) = '1' then
04044         trig_rate_AtoC <= trig_rate_AtoC + 1;
04045       end if;
04046     end if;
04047   end process trigger_rate_5;

[Process]
trigger_rate_6a ( BCLK ,
RESET )

trigger rates

Definition at line 4050 of file rio2mem.vhd.

04050   trigger_rate_6a : process (BCLK, RESET)
04051   begin  -- process trigger_rate_1
04052     if RESET = '1' then                   -- asynchronous reset (active high)
04053       trig_rate_Mult1A <= (others => '0');
04054     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04055       if (ctp_int(4) = '1') and (ctp_int(5) = '0') then
04056         trig_rate_Mult1A <= trig_rate_Mult1A + 1;
04057       end if;
04058     end if;
04059   end process trigger_rate_6a;

[Process]
trigger_rate_6c ( BCLK ,
RESET )

trigger rates

Definition at line 4086 of file rio2mem.vhd.

04086   trigger_rate_6c : process (BCLK, RESET)
04087   begin  -- process trigger_rate_1
04088     if RESET = '1' then                   -- asynchronous reset (active high)
04089       trig_rate_Mult1C <= (others => '0');
04090     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04091       if (ctp_int(6) = '1') and (ctp_int(7) = '0') then
04092         trig_rate_Mult1C <= trig_rate_Mult1C + 1;
04093       end if;
04094     end if;
04095   end process trigger_rate_6c;

[Process]
trigger_rate_7a ( BCLK ,
RESET )

trigger rates

Definition at line 4062 of file rio2mem.vhd.

04062   trigger_rate_7a : process (BCLK, RESET)
04063   begin  -- process trigger_rate_1
04064     if RESET = '1' then                   -- asynchronous reset (active high)
04065       trig_rate_Mult2A <= (others => '0');
04066     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04067       if (ctp_int(4) = '0') and (ctp_int(5) = '1') then
04068         trig_rate_Mult2A <= trig_rate_Mult2A + 1;
04069       end if;
04070     end if;
04071   end process trigger_rate_7a;

[Process]
trigger_rate_7c ( BCLK ,
RESET )

trigger rates

Definition at line 4098 of file rio2mem.vhd.

04098   trigger_rate_7c : process (BCLK, RESET)
04099   begin  -- process trigger_rate_1
04100     if RESET = '1' then                   -- asynchronous reset (active high)
04101       trig_rate_Mult2C <= (others => '0');
04102     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04103       if (ctp_int(6) = '0') and (ctp_int(7) = '1') then
04104         trig_rate_Mult2C <= trig_rate_Mult2C + 1;
04105       end if;
04106     end if;
04107   end process trigger_rate_7c;

[Process]
trigger_rate_8a ( BCLK ,
RESET )

trigger rates

Definition at line 4074 of file rio2mem.vhd.

04074   trigger_rate_8a : process (BCLK, RESET)
04075   begin  -- process trigger_rate_1
04076     if RESET = '1' then                   -- asynchronous reset (active high)
04077       trig_rate_Mult3pA <= (others => '0');
04078     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04079       if (ctp_int(4) = '1') and (ctp_int(5) = '1') then
04080         trig_rate_Mult3pA <= trig_rate_Mult3pA + 1;
04081       end if;
04082     end if;
04083   end process trigger_rate_8a;

[Process]
trigger_rate_8c ( BCLK ,
RESET )

trigger rates

Definition at line 4110 of file rio2mem.vhd.

04110   trigger_rate_8c : process (BCLK, RESET)
04111   begin  -- process trigger_rate_1
04112     if RESET = '1' then                   -- asynchronous reset (active high)
04113       trig_rate_Mult3pC <= (others => '0');
04114     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04115       if (ctp_int(6) = '1') and (ctp_int(7) = '1') then
04116         trig_rate_Mult3pC <= trig_rate_Mult3pC + 1;
04117       end if;
04118     end if;
04119   end process trigger_rate_8c;

Member Data Documentation

abort_contr abort_controller [Component Instantiation]

internal beam abort logic

Definition at line 4235 of file rio2mem.vhd.

acka_extend extend_test [Component Instantiation]

extend command for slower clock domains

Definition at line 2954 of file rio2mem.vhd.

ackb_extend extend_test [Component Instantiation]

extend command for slower clock domains

Definition at line 2980 of file rio2mem.vhd.

acki_extend extend_test [Component Instantiation]

extend command for slower clock domains

Definition at line 2967 of file rio2mem.vhd.

ackw_extend extend_test [Component Instantiation]

extend command for slower clock domains

Definition at line 2941 of file rio2mem.vhd.

algo_a delta_t_ac_top [Component Instantiation]

Algo A: 1-to-1 coincidence between side A & C within time window.

Definition at line 1139 of file rio2mem.vhd.

algo_b delta_t_ac_top [Component Instantiation]

Algo B: 2-to-2 coincidence between side A & C within time window.

Definition at line 1184 of file rio2mem.vhd.

algo_c delta_t_ac_top [Component Instantiation]

Algo C: One hit within time window.

Definition at line 1229 of file rio2mem.vhd.

algo_d delta_t_ac_top [Component Instantiation]

Algo D: Two hits within time window.

Definition at line 1274 of file rio2mem.vhd.

bunch_counter BID_cnt [Component Instantiation]

Bunch Crossing counter

Definition at line 3291 of file rio2mem.vhd.

busy_extend extend_test [Component Instantiation]

extend BUSY for minimum 8 BCs

Definition at line 3475 of file rio2mem.vhd.

chipscope_cntr icon [Component Instantiation]

Chipscope.

Chipscope Controller

Definition at line 4322 of file rio2mem.vhd.

chipscope_probe1 ila [Component Instantiation]

Chipscope ILA

Definition at line 4330 of file rio2mem.vhd.

chipscope_probe2 ila [Component Instantiation]

Chipscope ILA

Definition at line 4340 of file rio2mem.vhd.

chipscope_probe3 ila [Component Instantiation]

Chipscope ILA

Definition at line 4368 of file rio2mem.vhd.

CIBU cibu_comm [Component Instantiation]

CIBU (machine beam abort system) interface

Definition at line 4191 of file rio2mem.vhd.

clk_hz_sync edge [Component Instantiation]

sync 1 sec signal

Definition at line 2198 of file rio2mem.vhd.

command_extend1 extend_test [Component Instantiation]

Time win upper side A, A to C.

Time win lower side A, A to C Time win upper side C, A to C Time win lower side C, A to C Time win upper side A, C to A Time win lower side A, C to A Time win upper side C, C to A Time win lower side C, C to A Time win upper side A, wide Time win lower side A, wide Time win upper side C, wide Time win lower side C, wideextend command for slower clock domains

Definition at line 3958 of file rio2mem.vhd.

command_extend11 extend_test [Component Instantiation]

extend command for slower clock domains

Definition at line 3652 of file rio2mem.vhd.

command_extend12 extend_test [Component Instantiation]

extend command for slower clock domains

Definition at line 3708 of file rio2mem.vhd.

command_extend2 extend_test [Component Instantiation]

extend command for slower clock domains

Definition at line 4126 of file rio2mem.vhd.

command_extend21 extend_test [Component Instantiation]

extend command for slower clock domains

Definition at line 3680 of file rio2mem.vhd.

command_extend3 extend_test [Component Instantiation]

extend command for slower clock domains

Definition at line 4139 of file rio2mem.vhd.

command_extend6 extend_test [Component Instantiation]

extend command for slower clock domains

Definition at line 3801 of file rio2mem.vhd.

command_extend7 extend_test [Component Instantiation]

extend command for slower clock domains

Definition at line 3814 of file rio2mem.vhd.

command_extend8 extend_test [Component Instantiation]

extend command for slower clock domains

Definition at line 3827 of file rio2mem.vhd.

command_extend9 extend_test [Component Instantiation]

extend command for slower clock domains

Definition at line 3840 of file rio2mem.vhd.

command_extend_bcr_force extend_test [Component Instantiation]

extend bcr force

Definition at line 3736 of file rio2mem.vhd.

command_extend_ecr extend_test [Component Instantiation]

extend l1a_load

extend ecr_load

Definition at line 3666 of file rio2mem.vhd.

command_extend_ecr_force extend_test [Component Instantiation]

extend ecr force

Definition at line 3749 of file rio2mem.vhd.

command_extend_orb extend_test [Component Instantiation]

extend l1a_load

Definition at line 3694 of file rio2mem.vhd.

complete_extend extend_test [Component Instantiation]

extend readout complete pulse for slower clock domains

Definition at line 1650 of file rio2mem.vhd.

control0_i std_logic_vector ( 35 downto 0 ) [Signal]

signals for Chipscope Cores

Definition at line 862 of file rio2mem.vhd.

control1_i std_logic_vector ( 35 downto 0 ) [Signal]

signals for Chipscope Cores

Definition at line 862 of file rio2mem.vhd.

control2_i std_logic_vector ( 35 downto 0 ) [Signal]

signals for Chipscope Cores

Definition at line 862 of file rio2mem.vhd.

countddr2reads cnt_ddr2_rd [Component Instantiation]

count read accesses to ddr2

Definition at line 2125 of file rio2mem.vhd.

countddrreads cnt_ddr_rd [Component Instantiation]

count read accesses to ddr

Definition at line 1863 of file rio2mem.vhd.

CTP_intf ctp_comm [Component Instantiation]

CTP interface

Definition at line 3978 of file rio2mem.vhd.

ctplogic ctp_logic [Component Instantiation]

CTP logic

Definition at line 3904 of file rio2mem.vhd.

daq rios_all [Component Instantiation]

DAQ RocketIOs with support logic & data processing
In this module are all DAQ RocketIOs & their support logic. Also the rising edge timing information & the pulse widths are determined in here.

Definition at line 920 of file rio2mem.vhd.

dcs_bufr BUFR [Component Instantiation]

DCS collector clock.

Definition at line 3090 of file rio2mem.vhd.

dcs_msg_ctor status_collector [Component Instantiation]

DCS status msg collector

Definition at line 3110 of file rio2mem.vhd.

ddr2_clr_extend extend_test [Component Instantiation]

apply clr signal

Definition at line 2180 of file rio2mem.vhd.

ddr2_eth_buf eth_buf [Component Instantiation]

BRAM Buffer between DDR2 & EMAC, can hold data for 2 pkts

Definition at line 2149 of file rio2mem.vhd.

ddr2_udp_chksum_1 ddr2_chksum_cal [Component Instantiation]

UDP checksum calculation

Definition at line 2165 of file rio2mem.vhd.

ddr_clr_extend extend_test [Component Instantiation]

apply clr signal

Definition at line 1918 of file rio2mem.vhd.

ddr_udp_chksum_1 ddr_chksum_cal [Component Instantiation]

UDP checksum calculation

Definition at line 1903 of file rio2mem.vhd.

ddreth_buf ddr_eth_buf [Component Instantiation]

BRAM Buffer between DDR & EMAC, can hold data for 2 pkts

Definition at line 1887 of file rio2mem.vhd.

eth ethernet_top [Component Instantiation]

EMAC top module

Definition at line 2483 of file rio2mem.vhd.

fsm_encoding string [Attribute]

configs for timewindows

FSM encoding strategy

Definition at line 892 of file rio2mem.vhd.

int_beam_permit std_logic := ' 1 ' [Signal]

default to '1' !!!

Definition at line 531 of file rio2mem.vhd.

int_inj_permit std_logic := ' 1 ' [Signal]

default to '1' !!!

Definition at line 532 of file rio2mem.vhd.

intime_cuts intime [Component Instantiation]

time windows & coincidences

Definition at line 1355 of file rio2mem.vhd.

IOBUF_inst IOBUF [Component Instantiation]

no DDR RAM

Bidirectional buffer

Definition at line 1938 of file rio2mem.vhd.

IOBUF_inst2 IOBUF [Component Instantiation]

Bidirectional buffer.

Definition at line 1948 of file rio2mem.vhd.

L1A_delay bcm_signal_delay [Component Instantiation]

delay L1A

Definition at line 3263 of file rio2mem.vhd.

l1a_force_extend extend_test [Component Instantiation]

extend command for slower clock domains

Definition at line 2920 of file rio2mem.vhd.

l1a_force_sync edge [Component Instantiation]

sync command

Definition at line 2933 of file rio2mem.vhd.

l1a_sync edge [Component Instantiation]

sync L1A

Definition at line 3283 of file rio2mem.vhd.

latency_bcr_delay bcm_signal_delay [Component Instantiation]

delay latency bcr

Definition at line 3273 of file rio2mem.vhd.

Level_1_trigger_fifo l1a_fifo [Component Instantiation]

buffer L1As and respective BCIDs

Definition at line 3300 of file rio2mem.vhd.

ltp_rcd ltp_comm [Component Instantiation]

LTP interface

Definition at line 3776 of file rio2mem.vhd.

mask_err_n_i std_logic_vector ( 7 downto 0 ) := ( others = > ' 1 ' ) [Signal]

default to '1'!!!

Definition at line 730 of file rio2mem.vhd.

mask_i std_logic_vector ( 7 downto 0 ) := ( others = > ' 1 ' ) [Signal]

default to 1!!!

Definition at line 637 of file rio2mem.vhd.

mem_reset_extend extend_test [Component Instantiation]

extend reset pulse for slower clock domains

Definition at line 1637 of file rio2mem.vhd.

next_l1a std_logic := ' 1 ' [Signal]

default to 1!!!

Definition at line 444 of file rio2mem.vhd.

OBUF_inst OBUF [Component Instantiation]

Output buffer.

Definition at line 1958 of file rio2mem.vhd.

OBUF_inst10 OBUF [Component Instantiation]

Output buffer.

Definition at line 2018 of file rio2mem.vhd.

OBUF_inst2 OBUF [Component Instantiation]

Output buffer.

Definition at line 1966 of file rio2mem.vhd.

OBUF_inst3 OBUF [Component Instantiation]

Output buffer.

Definition at line 1973 of file rio2mem.vhd.

OBUF_inst4 OBUF [Component Instantiation]

Output buffer.

Definition at line 1979 of file rio2mem.vhd.

OBUF_inst5 OBUF [Component Instantiation]

Output buffer.

Definition at line 1985 of file rio2mem.vhd.

OBUF_inst6 OBUF [Component Instantiation]

Output buffer.

Definition at line 1991 of file rio2mem.vhd.

OBUF_inst7 OBUF [Component Instantiation]

Output buffer.

Definition at line 1997 of file rio2mem.vhd.

OBUF_inst8 OBUF [Component Instantiation]

Output buffer.

Output buffer

Definition at line 2005 of file rio2mem.vhd.

OBUF_inst9 OBUF [Component Instantiation]

Output buffer.

Definition at line 2012 of file rio2mem.vhd.

Orbit_delay bcm_signal_delay [Component Instantiation]

delay Orbit

Definition at line 3762 of file rio2mem.vhd.

PC_decoder command_decoder [Component Instantiation]

decode commands from PC

Definition at line 2612 of file rio2mem.vhd.

pktdone_extend extend_test [Component Instantiation]

extend pktdone

Definition at line 2387 of file rio2mem.vhd.

proc_buffer ddr_data_buffer [Component Instantiation]

buffer between RocketIOs & DDR RAM

Definition at line 1813 of file rio2mem.vhd.

proc_data_gen proc_data_emul [Component Instantiation]

data generation for ddr

Definition at line 1113 of file rio2mem.vhd.

proc_memory ram_user_backend [Component Instantiation]

DDR RAM top module

Definition at line 1827 of file rio2mem.vhd.

rate_reset_extend extend_test [Component Instantiation]

extend command for slower clock domains

Definition at line 3027 of file rio2mem.vhd.

raw_buffer ddr2_data_buffer [Component Instantiation]

buffer 200 MHz for DDR2

buffer between RocketIOs & DDR2 RAM

Definition at line 2072 of file rio2mem.vhd.

raw_data_gen raw_data_emul [Component Instantiation]

data generation for ddr2

Definition at line 1095 of file rio2mem.vhd.

raw_memory ddr2_usr_be [Component Instantiation]

DDR2 RAM top module

Definition at line 2086 of file rio2mem.vhd.

rd_ovr_sync edge [Component Instantiation]

synchronize rd_ovr pulse

Definition at line 2550 of file rio2mem.vhd.

rd_rdy_sync edge [Component Instantiation]

synchronize rd_rdy pulse

Definition at line 2529 of file rio2mem.vhd.

READ_OVER_extend extend_test [Component Instantiation]

extend READ_OVER pulse for slower clock domain

Definition at line 2537 of file rio2mem.vhd.

reset_extend extend_test [Component Instantiation]

extend command for slower clock domains

Definition at line 3014 of file rio2mem.vhd.

rio_reset_extend extend_test [Component Instantiation]

extend command for slower clock domains

Definition at line 3042 of file rio2mem.vhd.

rod bcm_rod [Component Instantiation]

ROD top module

Definition at line 3501 of file rio2mem.vhd.

rod_command_extend1 extend_test [Component Instantiation]

extend command for slower clock domains

Definition at line 3426 of file rio2mem.vhd.

rod_command_extend2 extend_test [Component Instantiation]

extend command for slower clock domains

Definition at line 3447 of file rio2mem.vhd.

rod_command_sync1 edge [Component Instantiation]

sync command

Definition at line 3439 of file rio2mem.vhd.

rod_command_sync2 edge [Component Instantiation]

sync command

Definition at line 3460 of file rio2mem.vhd.

safe_implementation string [Attribute]

force FSM safety logic implementation

Definition at line 895 of file rio2mem.vhd.

sata_wrapper bridge [Component Instantiation]

SATA top module

Definition at line 4261 of file rio2mem.vhd.

sl_end_force_extend extend_test [Component Instantiation]

extend command for slower clock domains

Definition at line 2907 of file rio2mem.vhd.

sl_ldown_i std_logic := ' 1 ' [Signal]

default to 1!!!

Definition at line 443 of file rio2mem.vhd.

sl_lff_i std_logic := ' 1 ' [Signal]

default to 1!!!

Definition at line 442 of file rio2mem.vhd.

start_extend extend_test [Component Instantiation]

extend the start_rdout pulse

Definition at line 2364 of file rio2mem.vhd.

start_run_extend extend_test [Component Instantiation]

extend command for slower clock domains

Definition at line 2993 of file rio2mem.vhd.

start_run_sync edge [Component Instantiation]

sync command

Definition at line 3006 of file rio2mem.vhd.

TDAQ_LVL1_buf lvl1_buf [Component Instantiation]

BRAM buffer for TDAQ data

Definition at line 3243 of file rio2mem.vhd.

The documentation for this class was generated from the following file:
Author: M.Niegl
Generated on Tue Nov 4 00:59:20 2008 for BCM-AAA by doxygen 1.5.7.1-20081012