ddr2_mem_infrastructure_iobs_0 Entity Reference
DDR clock IOBs. More...
Inheritance diagram for ddr2_mem_infrastructure_iobs_0:
Collaboration diagram for ddr2_mem_infrastructure_iobs_0:
Architectures | |
| arc_infrastructure_iobs | Architecture |
| DDR Clock IOBs. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| unisim | |
| Library with Xilinx primitives. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
| numeric_std | |
| arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
| ddr2_mem_parameters_0 | Package <ddr2_mem_parameters_0> |
| vcomponents | |
| Header with Xilinx primitives. | |
Ports | |
| CLK | in std_logic |
| clock | |
| DDR_CK | out std_logic |
| DDR clock pos. | |
| DDR_CK_N | out std_logic |
| DDR clock neg. | |
Detailed Description
DDR clock IOBs.The DDR2 memory clocks are generated here using the differential buffers and the ODDR elemnts in the IOBs.
Definition at line 42 of file ddr2_mem_infrastructure_iobs_0.vhd.
Member Data Documentation
CLK in std_logic [Port] |
DDR_CK out std_logic [Port] |
DDR_CK_N out std_logic [Port] |
ieee library [Library] |
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 30 of file ddr2_mem_infrastructure_iobs_0.vhd.
std_logic_1164 package [Package] |
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 28 of file ddr2_mem_infrastructure_iobs_0.vhd.
unisim library [Library] |
vcomponents package [Package] |
The documentation for this class was generated from the following file:
