ddr2_mem_pattern_compare8.arc_pattern_compare Architecture Reference

DDR2 pattern compare. More...

Inheritance diagram for ddr2_mem_pattern_compare8.arc_pattern_compare:

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Collaboration diagram for ddr2_mem_pattern_compare8.arc_pattern_compare:

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List of all members.

Processes
PROCESS_125	( clk )
	read enable shift
PROCESS_126	( clk )
	done flag FF
PROCESS_127	( clk )
	read enable rising edge data MUX
PROCESS_128	( clk )
	read enable falling edge data MUX
PROCESS_129	( clk )
	data FFs
PROCESS_130	( clk )
	read enable FF
PROCESS_131	( clk )
	first flag FF
PROCESS_132	( clk )
	rise data
PROCESS_133	( clk )
	FSM state transitions.
PROCESS_134	( cntrl_rden_r , rise_state , rd_data_rise_r , rst )
	FSM.
PROCESS_135	( clk )
	fall data
PROCESS_136	( clk )
	FSM state transitions.
PROCESS_137	( cntrl_rden_r , fall_state , rd_data_fall_r , rst )
	FSM.
Signals
rise_next_state	state_machine1
rise_state	state_machine1
fall_next_state	state_machine2
fall_state	state_machine2
clk_cnt_rise	std_logic_vector ( 3 downto 0 )
clk_cnt_fall	std_logic_vector ( 3 downto 0 )
clk_count_rise	std_logic_vector ( 3 downto 0 )
clk_count_fall	std_logic_vector ( 3 downto 0 )
cntrl_rden_r	std_logic
rd_data_rise_r	std_logic_vector ( 7 downto 0 )
rd_data_fall_r	std_logic_vector ( 7 downto 0 )
rd_en_r1	std_logic
rd_en_r2	std_logic
rd_en_r3	std_logic
rd_en_r4	std_logic
rd_en_r5	std_logic
rd_en_r6	std_logic
rd_en_r7	std_logic
rd_en_r8	std_logic
rd_en_r9	std_logic
rd_en_r10	std_logic
comp_done0	std_logic
comp_done_r	std_logic

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Detailed Description

DDR2 pattern compare.

Compares the IOB output 8 bit data of one bank that is read data during the intilaization to get the delay for the data with respect to the command issued.

Definition at line 71 of file ddr2_mem_pattern_compare8.vhd.

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Member Function Documentation

[Process]

PROCESS_125

( clk )

read enable shift

Definition at line 100 of file ddr2_mem_pattern_compare8.vhd.

  process(clk)
  begin
    if (clk = '1' and clk'event) then
      if (rst = '1') then
        rd_en_r1  <= '0';
        rd_en_r2  <= '0';
        rd_en_r3  <= '0';
        rd_en_r4  <= '0';
        rd_en_r5  <= '0';
        rd_en_r6  <= '0';
        rd_en_r7  <= '0';
        rd_en_r8  <= '0';
        rd_en_r9  <= '0';
        rd_en_r10 <= '0';
      else
        rd_en_r1  <= ctrl_rden;
        rd_en_r2  <= rd_en_r1;
        rd_en_r3  <= rd_en_r2;
        rd_en_r4  <= rd_en_r3;
        rd_en_r5  <= rd_en_r4;
        rd_en_r6  <= rd_en_r5;
        rd_en_r7  <= rd_en_r6;
        rd_en_r8  <= rd_en_r7;
        rd_en_r9  <= rd_en_r8;
        rd_en_r10 <= rd_en_r9;
      end if;
    end if;
  end process;

[Process]

PROCESS_126

( clk )

done flag FF

Definition at line 130 of file ddr2_mem_pattern_compare8.vhd.

  process(clk)
  begin
    if (clk = '1' and clk'event) then
      if (rst = '1') then
        comp_done_r <= '0';
      else
        comp_done_r <= comp_done0;
      end if;
    end if;
  end process;

[Process]

PROCESS_127

( clk )

read enable rising edge data MUX

Definition at line 142 of file ddr2_mem_pattern_compare8.vhd.

  process(clk)
  begin
    if (clk = '1' and clk'event) then
      if (rst = '1') then
        rd_en_rise <= '0';
      elsif(comp_done_r = '1') then
        case clk_count_rise is
          when "0011" => rd_en_rise <= rd_en_r2;
          when "0100" => rd_en_rise <= rd_en_r3;
          when "0101" => rd_en_rise <= rd_en_r4;
          when "0110" => rd_en_rise <= rd_en_r5;
          when "0111" => rd_en_rise <= rd_en_r6;
          when "1000" => rd_en_rise <= rd_en_r7;
          when "1001" => rd_en_rise <= rd_en_r8;
          when others => rd_en_rise <= '0';
        end case;
      end if;
    end if;
  end process;

[Process]

PROCESS_128

( clk )

read enable falling edge data MUX

Definition at line 163 of file ddr2_mem_pattern_compare8.vhd.

  process(clk)
  begin
    if (clk = '1' and clk'event) then
      if (rst = '1') then
        rd_en_fall <= '0';
      elsif(comp_done_r = '1') then
        case (clk_count_fall) is
          when "0011" => rd_en_fall <= rd_en_r2;
          when "0100" => rd_en_fall <= rd_en_r3;
          when "0101" => rd_en_fall <= rd_en_r4;
          when "0110" => rd_en_fall <= rd_en_r5;
          when "0111" => rd_en_fall <= rd_en_r6;
          when "1000" => rd_en_fall <= rd_en_r7;
          when "1001" => rd_en_fall <= rd_en_r8;
          when others => rd_en_fall <= '0';
        end case;
      end if;
    end if;
  end process;

[Process]

PROCESS_129

( clk )

data FFs

Definition at line 186 of file ddr2_mem_pattern_compare8.vhd.

  process(clk)
  begin
    if (clk = '1' and clk'event) then
      if (rst = '1') then
        rd_data_rise_r <= (others => '0');
        rd_data_fall_r <= (others => '0');
      else
        rd_data_rise_r <= rd_data_rise;
        rd_data_fall_r <= rd_data_fall;
      end if;
    end if;
  end process;

[Process]

PROCESS_130

( clk )

read enable FF

Definition at line 200 of file ddr2_mem_pattern_compare8.vhd.

  process(clk)
  begin
    if (clk = '1' and clk'event) then
      if (rst = '1') then
        cntrl_rden_r <= '0';
      else
        cntrl_rden_r <= ctrl_rden;
      end if;
    end if;
  end process;

[Process]

PROCESS_131

( clk )

first flag FF

Definition at line 212 of file ddr2_mem_pattern_compare8.vhd.

  process(clk)
  begin
    if (clk = '1' and clk'event) then
      if (rst = '1') then
        first_rising <= '0';
      elsif(rise_state = rise_first_data and rd_data_rise_r = X"55") then
        first_rising <= '1';
      end if;
    end if;
  end process;

[Process]

PROCESS_132

( clk )

rise data

Definition at line 226 of file ddr2_mem_pattern_compare8.vhd.

  process(clk)
  begin
    if (clk = '1' and clk'event) then
      if (rst = '1') then
        clk_cnt_rise <= (others => '0');
      elsif(rise_state = rise_first_data) then
        clk_cnt_rise <= clk_cnt_rise + "0001";
      else
        clk_cnt_rise <= clk_cnt_rise;
      end if;
    end if;
  end process;

[Process]

PROCESS_133

( clk )

FSM state transitions.

Definition at line 240 of file ddr2_mem_pattern_compare8.vhd.

  process(clk)
  begin
    if (clk = '1' and clk'event) then
      if (rst = '1') then
        rise_state <= rise_idle;
      else
        rise_state <= rise_next_state;
      end if;
    end if;
  end process;

[Process]

PROCESS_134		( cntrl_rden_r ,
		rise_state ,
		rd_data_rise_r ,
		rst )

FSM.

Definition at line 252 of file ddr2_mem_pattern_compare8.vhd.

  process(cntrl_rden_r, rise_state, rd_data_rise_r, rst)
  begin
    if (rst = '1') then
      rise_next_state <= rise_idle;
    else
      case (rise_state) is
        when rise_idle =>
          if(cntrl_rden_r = '1') then
            rise_next_state <= rise_first_data;
          else
            rise_next_state <= rise_idle;
          end if;
          
        when rise_first_data =>
          if((rd_data_rise_r = X"AA") or (rd_data_rise_r = X"55")) then
            rise_next_state <= rise_comp_over;  --second_data
          else
            rise_next_state <= rise_first_data;
          end if;

        when rise_second_data =>
          if((rd_data_rise_r = X"99") or (rd_data_rise_r = X"66")) then
            rise_next_state <= rise_comp_over;
          else
            rise_next_state <= rise_first_data;
          end if;

        when rise_comp_over =>
          rise_next_state <= rise_comp_over;
          
        when others =>
          rise_next_state <= rise_idle;
          
      end case;
    end if;
  end process;

[Process]

PROCESS_135

( clk )

fall data

Definition at line 292 of file ddr2_mem_pattern_compare8.vhd.

  process(clk)
  begin
    if (clk = '1' and clk'event) then
      if (rst = '1') then
        clk_cnt_fall <= "0000";
      elsif(fall_state = fall_first_data) then
        clk_cnt_fall <= clk_cnt_fall + "0001";
      else
        clk_cnt_fall <= clk_cnt_fall;
      end if;
    end if;
  end process;

[Process]

PROCESS_136

( clk )

FSM state transitions.

Definition at line 306 of file ddr2_mem_pattern_compare8.vhd.

  process(clk)
  begin
    if (clk = '1' and clk'event) then
      if (rst = '1') then
        fall_state <= fall_idle;
      else
        fall_state <= fall_next_state;
      end if;
    end if;
  end process;

[Process]

PROCESS_137		( cntrl_rden_r ,
		fall_state ,
		rd_data_fall_r ,
		rst )

FSM.

Definition at line 318 of file ddr2_mem_pattern_compare8.vhd.

  process(cntrl_rden_r, fall_state, rd_data_fall_r, rst)
  begin
    if(rst = '1') then
      fall_next_state <= fall_idle;
    else
      case (fall_state) is
        when fall_idle =>
          if(cntrl_rden_r = '1') then
            fall_next_state <= fall_first_data;
          else
            fall_next_state <= fall_idle;
          end if;
          
          
        when fall_first_data =>
          if((rd_data_fall_r = X"55") or (rd_data_fall_r = X"AA")) then
            fall_next_state <= fall_comp_over;  --second_data
          else
            fall_next_state <= fall_first_data;
          end if;

        when fall_second_data =>
          if((rd_data_fall_r = X"66") or (rd_data_fall_r = X"99")) then
            fall_next_state <= fall_comp_over;
          else
            fall_next_state <= fall_first_data;
          end if;

        when fall_comp_over =>
          fall_next_state <= fall_comp_over;
          
        when others =>
          fall_next_state <= fall_idle;
          
      end case;
    end if;
  end process;

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The documentation for this class was generated from the following file:

• ddr2_mem_pattern_compare8.vhd