ddr2_mem_user_interface_0.user_interface_arc Architecture Reference

DDR2 controller user interface. More...

Inheritance diagram for ddr2_mem_user_interface_0.user_interface_arc:

Inheritance graph
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Collaboration diagram for ddr2_mem_user_interface_0.user_interface_arc:

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List of all members.


Components

ddr2_mem_rd_data_0  <Entity ddr2_mem_rd_data_0>
 read data FIFOs & logic
ddr2_mem_backend_fifos_0  <Entity ddr2_mem_backend_fifos_0>
 Back-End FIFOs.

Signals

read_data_fifo_rise_i  std_logic_vector ( dq_width-1 downto 0 )
read_data_fifo_fall_i  std_logic_vector ( dq_width-1 downto 0 )

Component Instantiations

rd_data_00 ddr2_mem_rd_data_0 <Entity ddr2_mem_rd_data_0>
 read data FIFOs & logic
backend_fifos_00 ddr2_mem_backend_fifos_0 <Entity ddr2_mem_backend_fifos_0>
 Back-End FIFOs.


Detailed Description

DDR2 controller user interface.

This module interfaces with the user. The user should provide the data and various commands.

Definition at line 90 of file ddr2_mem_user_interface_0.vhd.


Member Data Documentation

backend_fifos_00 ddr2_mem_backend_fifos_0 [Component Instantiation]

Back-End FIFOs.

Definition at line 155 of file ddr2_mem_user_interface_0.vhd.

Back-End FIFOs.

Definition at line 108 of file ddr2_mem_user_interface_0.vhd.

ddr2_mem_rd_data_0 [Component]

read data FIFOs & logic

Definition at line 93 of file ddr2_mem_user_interface_0.vhd.

rd_data_00 ddr2_mem_rd_data_0 [Component Instantiation]

read data FIFOs & logic

Definition at line 141 of file ddr2_mem_user_interface_0.vhd.


The documentation for this class was generated from the following file:

Author: M.Niegl
Generated on Tue Nov 4 00:50:51 2008 for BCM-AAA by doxygen 1.5.7.1-20081012