Components | |
ddr2_mem_rd_data_0 | <Entity ddr2_mem_rd_data_0> |
read data FIFOs & logic | |
ddr2_mem_backend_fifos_0 | <Entity ddr2_mem_backend_fifos_0> |
Back-End FIFOs. | |
Signals | |
read_data_fifo_rise_i | std_logic_vector ( dq_width-1 downto 0 ) |
read_data_fifo_fall_i | std_logic_vector ( dq_width-1 downto 0 ) |
Component Instantiations | |
rd_data_00 | ddr2_mem_rd_data_0 <Entity ddr2_mem_rd_data_0> |
read data FIFOs & logic | |
backend_fifos_00 | ddr2_mem_backend_fifos_0 <Entity ddr2_mem_backend_fifos_0> |
Back-End FIFOs. |
This module interfaces with the user. The user should provide the data and various commands.
Definition at line 90 of file ddr2_mem_user_interface_0.vhd.
backend_fifos_00 ddr2_mem_backend_fifos_0 [Component Instantiation] |
ddr2_mem_backend_fifos_0 [Component] |
ddr2_mem_rd_data_0 [Component] |
rd_data_00 ddr2_mem_rd_data_0 [Component Instantiation] |