raw_buffer Entity Reference
Wrapper for BRAM Buffer between RIOs and DDR2.
More...
List of all members.
|
Architectures |
| raw_buffer_a | Architecture |
| | Wrapper for BRAM Buffer between RIOs and DDR2. More...
|
Libraries |
| ieee | |
| | standard IEEE library
|
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XilinxCoreLib | |
Packages |
| std_logic_1164 | |
| | std_logic definitions, see file
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Ports |
| addra | in ( 6 downto 0 ) |
| | Read address.
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| addrb | in ( 5 downto 0 ) |
| | Write address.
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| clka | in |
| | Read clock.
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| clkb | in |
| | Write clock.
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| dinb | in ( 255 downto 0 ) |
| | Write data.
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| douta | out ( 127 downto 0 ) |
| | Read data.
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| ena | in |
| | Read enable.
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| enb | in |
| | Write port enable.
|
| web | in |
| | Write enable.
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Detailed Description
Wrapper for BRAM Buffer between RIOs and DDR2.
Definition at line 68 of file raw_buffer.vhd.
Member Data Documentation
addra in ( 6 downto 0 ) [Port] |
addrb in ( 5 downto 0 ) [Port] |
dinb in ( 255 downto 0 ) [Port] |
douta out ( 127 downto 0 ) [Port] |
The documentation for this class was generated from the following file:
