1.5.7.1-20081012| abort_buffer.vhd [code] | DPBRAM for abort logic |
| abort_controller.vhd [code] | Beam abort logic |
| addsub48.vhd [code] | Virtex-4 DSP48 Core Wrapper |
| auto_receiver.vhd [code] | Receives packets from EMAC & decodes packets |
| bcm_aaa.vhd [code] | Top module of BCM AAA design |
| bcm_emac_fifo.vhd [code] | Wrapper file of FIFO Core for Ethernet TX |
| bcm_emac_fifo_rx.vhd [code] | Wrapper file of FIFO Core for Ethernet RX |
| bcm_rod.vhd [code] | ROD formatter top module |
| bcm_rod_dp_ram.vhd [code] | DPRAM for ROD formatter |
| bcm_rod_dp_updown_counter.vhd [code] | Up-Down Counter |
| bcm_rod_formatter.vhd [code] | ROD formatter |
| bcm_rod_ram.vhd [code] | DPRAM wrapper |
| bcm_rod_slink.vhd [code] | S-Link interface |
| bcm_rod_treadmil.vhd [code] | ROD treadmill |
| bcm_signal_delay.vhd [code] | Flexible shift-register as delay unit |
| bcm_signal_delay_vec.vhd [code] | Flexible shift-register as delay unit for 32 bit vectors |
| BID_cnt.vhd [code] | Bunch-Counter |
| bridge.vhd [code] | Top module of SATA |
| buffer_3ST.vhd [code] | Tri-State Buffer |
| build_parameters.vhd [code] | Config parameters for building the project |
| bunchcycle.vhd [code] | Collects pulse information and groups it per bunch crossing |
| busy.vhd [code] | Busy module |
| cal.vhd [code] | Calculate pulse widths |
| cal_block_v1_4_1.vhd [code] | RocketIO calibration module |
| cibu_comm.vhd [code] | Interface to CIBU |
| clock_divider.vhd [code] | Prescaler |
| clocks.vhd [code] | Central clock module |
| cnt_ddr2_rd.vhd [code] | Counter for accesses to DDR2 |
| cnt_ddr_rd.vhd [code] | Counter for accesses to DDR |
| command_decoder.vhd [code] | Pc-controlled module inside the FPGA |
| comparator4.vhd [code] | 4-Input greatest value selector |
| comparator_v9_0.vhd [code] | Greater-than Comparator Core |
| ctp_comm.vhd [code] | Interface to CTP |
| ctp_logic.vhd [code] | Top module of logic for CTP bits |
| daq_header.vhd [code] | Functions used in DAQ modules |
| daqrio_top.vhd [code] | Top module of 2 full RIO chains |
| ddr2_chksum_cal.vhd [code] | Running DDR2 UDP chksum calculation |
| ddr2_data_buffer.vhd [code] | Interface between DAQ & DDR2 |
| ddr2_mem.vhd [code] | Structure of DDR2 Controller |
| ddr2_mem_backend_fifos_0.vhd [code] | DDR2 Back-End FIFOs |
| ddr2_mem_controller_iobs_0.vhd [code] | Control signal IOBs |
| ddr2_mem_data_path_0.vhd [code] | Calibration structure for data |
| ddr2_mem_data_path_iobs_0.vhd [code] | Datapath IOBs |
| ddr2_mem_data_tap_inc.vhd [code] | Tap logic |
| ddr2_mem_data_write_0.vhd [code] | Write data organizer |
| ddr2_mem_ddr2_controller.vhd [code] | Main RAM controller module |
| ddr2_mem_idelay_ctrl.vhd [code] | IDELAYCTRL primitives for DDR2 RAM |
| ddr2_mem_infrastructure.vhd [code] | Services for DDR2 memory controller |
| ddr2_mem_infrastructure_iobs_0.vhd [code] | DDR clock IOBs |
| ddr2_mem_iobs_0.vhd [code] | DDR2 IOBs |
| ddr2_mem_parameters_0.vhd [code] | Header file for DDR2 RAM controller |
| ddr2_mem_pattern_compare8.vhd [code] | DDR2 pattern compare |
| ddr2_mem_RAM_D_0.vhd [code] | DistRAM to buffer data |
| ddr2_mem_rd_data_0.vhd [code] | Read datapath |
| ddr2_mem_rd_data_fifo_0.vhd [code] | DistRAM for read data |
| ddr2_mem_rd_wr_addr_fifo_0.vhd [code] | FIFO for read/write address |
| ddr2_mem_tap_ctrl.vhd [code] | Tap control logic |
| ddr2_mem_tap_logic_0.vhd [code] | Data tap module |
| ddr2_mem_top_0.vhd [code] | Top module of DDR2 RAM controller |
| ddr2_mem_user_interface_0.vhd [code] | DDR2 controller user interface |
| ddr2_mem_v4_dm_iob.vhd [code] | DDR2 data mask IOBs |
| ddr2_mem_v4_dq_iob.vhd [code] | DDR2 data IOBs |
| ddr2_mem_v4_dqs_iob.vhd [code] | DDR2 data strobe IOBs |
| ddr2_mem_wr_data_fifo_16.vhd [code] | Write data FIFO |
| ddr2_usr_be.vhd [code] | Top module of DDR2 RAM controller |
| ddr_chksum_accu.vhd [code] | 32-bit DSP accumulator |
| ddr_chksum_adder.vhd [code] | 32-bit DSP adder |
| ddr_chksum_cal.vhd [code] | Running DDR UDP chksum calculation |
| ddr_data_buffer.vhd [code] | Interface between DAQ & DDR |
| ddr_eth_buf.vhd [code] | Buffer between DDR & EMAC |
| ddreth_buf.vhd [code] | Wrapper for BRAM Buffer between DDR and Ethernet |
| delay.vhd [code] | Delay unit |
| delay_adj.vhd [code] | Fine delay for 2 RocketIO channels |
| delta_t_ac_top.vhd [code] | Top module of time window & coincidence logic |
| division.vhd [code] | Division by constant power of two |
| dss_comm.vhd [code] | Interface to DSS |
| edge.vhd [code] | Edge detection module |
| edge_det.vhd [code] | Data edge detection |
| edge_fal.vhd [code] | Edge detection module |
| eth_buf.vhd [code] | Buffer between DDR2 and EMAC |
| ethbuf.vhd [code] | Wrapper for DPRAM Buffer core |
| ethernet_top.vhd [code] | Top module of Ethernet design part |
| EVENT_cnt.vhd [code] | ATLAS Level-1 Event Counter |
| extend_test.vhd [code] | Extending a pulse |
| generic_shift_reg.vhd [code] | Generic shift register |
| gt11_init_rx.vhd [code] | Initializer for RocketIO RX |
| gt11_init_tx.vhd [code] | Initializer for RocketIO TX |
| incrementer.vhd [code] | 32-bit incrementer with synchronous reset and latched output |
| intime.vhd [code] | Narrow in-time time window |
| ipmac.vhd [code] | Header with IP & MAC addresses |
| l1a_fifo.vhd [code] | FIFO core for L1As |
| LCD.vhd [code] | LCD wrapper |
| lcd_characters.vhd [code] | Constants declaration |
| lcd_commander.vhd [code] | LCD command unit |
| lcd_controller.vhd [code] | LCD controller |
| LFSR14_23A3.vhd [code] | Linear feedback shift register |
| loop_cnt.vhd [code] | Continous counter, 32 bit |
| loop_cnt_sh.vhd [code] | Continous counter, 6 bit |
| ltp_comm.vhd [code] | Interface to LTP |
| lvl1_buf.vhd [code] | Buffer for Level-1 TDAQ data |
| lvl1_circ_buffer.vhd [code] | DPBRAM buffer |
| main_components.vhd [code] | Declaration of all major components |
| mem_interface_top.vhd [code] | |
| mem_interface_top_backend_fifos_0.vhd [code] | |
| mem_interface_top_controller_iobs_0.vhd [code] | |
| mem_interface_top_data_path_0.vhd [code] | |
| mem_interface_top_data_path_iobs_0.vhd [code] | |
| mem_interface_top_data_tap_inc.vhd [code] | |
| mem_interface_top_data_write_0.vhd [code] | |
| mem_interface_top_ddr_controller_0.vhd [code] | |
| mem_interface_top_idelay_ctrl.vhd [code] | Virtex-4 IDELAYCTRL Wrapper |
| mem_interface_top_infrastructure.vhd [code] | DCM for DDR specific clocks |
| mem_interface_top_infrastructure_iobs_0.vhd [code] | |
| mem_interface_top_iobs_0.vhd [code] | |
| mem_interface_top_parameters_0.vhd [code] | Header file for DDR RAM controller |
| mem_interface_top_pattern_compare8.vhd [code] | |
| mem_interface_top_RAM_D_0.vhd [code] | |
| mem_interface_top_rd_data_0.vhd [code] | |
| mem_interface_top_rd_data_fifo_0.vhd [code] | |
| mem_interface_top_rd_wr_addr_fifo_0.vhd [code] | |
| mem_interface_top_tap_ctrl_0.vhd [code] | |
| mem_interface_top_tap_logic_0.vhd [code] | |
| mem_interface_top_top_0.vhd [code] | |
| mem_interface_top_user_interface_0.vhd [code] | |
| mem_interface_top_v4_dm_iob.vhd [code] | |
| mem_interface_top_v4_dq_iob.vhd [code] | |
| mem_interface_top_v4_dqs_iob.vhd [code] | |
| mem_interface_top_wr_data_fifo_16.vhd [code] | |
| mgt_clock_module.vhd [code] | Wrapper for RocketIO clock module |
| ncm_pac.vhd [code] | Header file for TEMAC wrapper |
| ncm_temac.vhd [code] | Interface to HW MAC |
| onescompaccu.vhd [code] | Accu with Carry Look-Ahead Adder |
| onescomplementadder.vhd [code] | Carry Look-Ahead Full-Adder |
| ORBIT_cnt.vhd [code] | Counter for LHC Machine Turns |
| period_check.vhd [code] | Check the period of signal |
| pmdelay.vhd [code] | Variable Post-Mortem layoff - orbit delay |
| prescaler.vhd [code] | Simple Prescaler |
| proc_data_buf.vhd [code] | Dual-Port BRAM Buffer customized for proc data |
| proc_data_emul.vhd [code] | Pattern generator to fill proc data buffers |
| ram_user_backend.vhd [code] | Top module of DDR RAM controller |
| raw_buffer.vhd [code] | Wrapper for BRAM Buffer between RIOs and DDR2 |
| raw_data_emul.vhd [code] | Pattern generator to fill raw data buffers |
| rio.vhd [code] | RocketIO wrapper |
| rio2mem.vhd [code] | Contains all major design modules (RAMs, RIO, EMAC) |
| rio_rxtx.vhd [code] | DAQ-RocketIO wrapper and support logic |
| riocheck.vhd [code] | Error detection module for RocketIOs, currently unused |
| rios_all.vhd [code] | Top module of RocketIOs & DAQ |
| rocketio_sata.vhd [code] | SATA RocketIO wrapper |
| sata.vhd [code] | SATA wrapper |
| sata_cal_block_v1_4_1.vhd [code] | SATA RIO calibration module |
| sata_gt11_init_rx.vhd [code] | RIO-RX initializer |
| sata_gt11_init_tx.vhd [code] | RIO-TX initializer |
| shift_reg.vhd [code] | Adjustable 32-bit wide shift register |
| side_4rios.vhd [code] | Combination of 2 RocketIO-pairs |
| statistics.vhd [code] | Determines minimum, maximum and average of a series of input values |
| status_collector.vhd [code] | Data collector for DCS status messages |
| tdaq_collector.vhd [code] | Data collector for TDAQ status messages |
| temac.vhd [code] | Virtex-4 FX Ethernet MAC Wrapper |
| temac_controller.vhd [code] | Support logic for EMAC |
| timewindow.vhd [code] | Apply time window to 1 channel |
| udp_addresses.vhd [code] | Header for Ethernet modules |
| univibrator.vhd [code] | Univibrator |
1.5.7.1-20081012