ctp_comm Entity Reference
Interface to CTP (Central Trigger Processor). More...
Inheritance diagram for ctp_comm:
Collaboration diagram for ctp_comm:
Architectures | |
| ctp_comm_arc | Architecture |
| Interface to CTP (Central Trigger Processor). More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
Ports | |
| CLK | in std_logic |
| Clock. | |
| RESET | in std_logic |
| Reset. | |
| SET_EN | in std_logic |
| Enable Setting of outputs. | |
| SET_VAL | in std_logic_vector ( 9 downto 1 ) |
| Value to be set. | |
| CTP_OUT | out std_logic_vector ( 9 downto 1 ) |
| Output to CTP. | |
Detailed Description
Interface to CTP (Central Trigger Processor).This entity provides an interface to the ATLAS CTP to which we provide 9 bits of input information per LHC bunch. It also provides the possibility of setting the output to a particular value.
Definition at line 34 of file ctp_comm.vhd.
Member Data Documentation
CLK in std_logic [Port] |
CTP_OUT out std_logic_vector ( 9 downto 1 ) [Port] |
ieee library [Library] |
RESET in std_logic [Port] |
SET_EN in std_logic [Port] |
SET_VAL in std_logic_vector ( 9 downto 1 ) [Port] |
std_logic_1164 package [Package] |
std_logic definitions, see file
Reimplemented in main_components.
Definition at line 27 of file ctp_comm.vhd.
The documentation for this class was generated from the following file:
