ddr2_mem_v4_dq_iob Entity Reference
DDR2 data IOBs. More...
Inheritance diagram for ddr2_mem_v4_dq_iob:
Collaboration diagram for ddr2_mem_v4_dq_iob:
Architectures | |
| arc_v4_dq_iob | Architecture |
| DDR2 data IOBs. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| unisim | |
| Library with Xilinx primitives. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
| numeric_std | |
| arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
| vcomponents | |
| Header with Xilinx primitives. | |
Ports | |
| CLK | in std_logic |
| clock | |
| CLK90 | in std_logic |
 phase-shifted clock | |
| CAL_CLK | in std_logic |
| calibration clock | |
| RESET | in std_logic |
| reset | |
| DATA_DLYINC | in std_logic |
| delay increment | |
| DATA_DLYCE | in std_logic |
| delay clock enable | |
| DATA_DLYRST | in std_logic |
| delay reset | |
| WRITE_DATA_RISE | in std_logic |
| rising edge data write | |
| WRITE_DATA_FALL | in std_logic |
| falling edge data write | |
| CTRL_WREN | in std_logic |
| control write enable | |
| DDR_DQ | inout std_logic |
| DDR IO to RAM. | |
| READ_DATA_RISE | out std_logic |
| rising edge data read | |
| READ_DATA_FALL | out std_logic |
| falling edge data read | |
Detailed Description
DDR2 data IOBs.This module places the data in the IOBs.
Definition at line 57 of file ddr2_mem_v4_dq_iob.vhd.
Member Data Documentation
CAL_CLK in std_logic [Port] |
CLK in std_logic [Port] |
CLK90 in std_logic [Port] |
CTRL_WREN in std_logic [Port] |
DATA_DLYCE in std_logic [Port] |
DATA_DLYINC in std_logic [Port] |
DATA_DLYRST in std_logic [Port] |
DDR_DQ inout std_logic [Port] |
ieee library [Library] |
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 49 of file ddr2_mem_v4_dq_iob.vhd.
READ_DATA_FALL out std_logic [Port] |
READ_DATA_RISE out std_logic [Port] |
RESET in std_logic [Port] |
std_logic_1164 package [Package] |
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 47 of file ddr2_mem_v4_dq_iob.vhd.
unisim library [Library] |
vcomponents package [Package] |
WRITE_DATA_FALL in std_logic [Port] |
WRITE_DATA_RISE in std_logic [Port] |
The documentation for this class was generated from the following file:
