statistics.statistics_arc Architecture Reference

Determines minimum, maximum and average of a series of input values. More...

Inheritance diagram for statistics.statistics_arc:

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Collaboration diagram for statistics.statistics_arc:

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List of all members.

Functions
integer	safe_div ( A: in integer )
	make sure divisor is a power of two
Processes
series_cnt	( CLK )
	count length of input series
minimum_cal	( CLK )
	determine minimum of series
maximum_cal	( CLK )
	determine maximum of series
avg_acc	( CLK )
Components
division	<Entity division>
	Division.
Constants
c_len	integer := safe_div ( SERIES_LENGTH )
	divisor
Signals
ser_end	std_logic := ' 0 '
res_int	std_logic := ' 0 '
minimum_reg	unsigned ( 15 downto 0 ) := ( others = > ' 0 ' )
maximum_reg	unsigned ( 15 downto 0 ) := ( others = > ' 0 ' )
average_reg	unsigned ( 15 downto 0 ) := ( others = > ' 0 ' )
accu_reg	unsigned ( 15 downto 0 ) := ( others = > ' 0 ' )
avg_in	unsigned ( 15 downto 0 ) := ( others = > ' 0 ' )
avg_out	unsigned ( 15 downto 0 ) := ( others = > ' 0 ' )
Component Instantiations
average_cal	division <Entity division>

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Detailed Description

Determines minimum, maximum and average of a series of input values.

This entity determines the minimum & maximum value as well as the average of a series of input values. The series length is specified via a generic that needs to be a power of two. A function makes sure this is garantueed.

Definition at line 54 of file statistics.vhd.

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Member Function Documentation

[Process]

maximum_cal

( CLK )

determine maximum of series

Definition at line 143 of file statistics.vhd.

  maximum_cal : process (CLK)
  begin  -- process minimum
    if CLK'event and CLK = '1' then     -- rising clock edge
      if res_int = '1' then
        maximum_reg <= unsigned(VAL);
      elsif unsigned(VAL) > maximum_reg then
        maximum_reg <= unsigned(VAL);
      else
        maximum_reg <= maximum_reg;
      end if;
    end if;
  end process maximum_cal;

[Process]

minimum_cal

( CLK )

determine minimum of series

Definition at line 127 of file statistics.vhd.

  minimum_cal : process (CLK)
  begin  -- process minimum
    if CLK'event and CLK = '1' then     -- rising clock edge
      if res_int = '1' then
        minimum_reg <= unsigned(VAL);
      elsif unsigned(VAL) <= minimum_reg then
        minimum_reg <= unsigned(VAL);
      else
        minimum_reg <= minimum_reg;
      end if;
    end if;
  end process minimum_cal;

[Function]

integer safe_div

( A in integer )

make sure divisor is a power of two

Definition at line 68 of file statistics.vhd.

  function safe_div (
    A : integer)
    return integer is
    variable Ai  : integer;
    variable ret : integer := 2;
  begin  -- safe_div
    Ai := A;
    while 0 < 1 loop
      if Ai < 2 then
        ret := 2;
        exit;
      else
        if Ai mod 2 /= 0 then
          Ai := Ai - 1;
        else
          ret := Ai;
          exit;
        end if;
      end if;
    end loop;
    return ret;
  end safe_div;

[Process]

series_cnt

( CLK )

count length of input series

Definition at line 108 of file statistics.vhd.

  series_cnt : process (CLK)
    variable cnt : integer := 0;
  begin  -- process series_cnt
    if CLK'event and CLK = '1' then     -- rising clock edge
      if RES = '1' then
        cnt     := 0;
        ser_end <= '0';
      else
        ser_end <= '0';
        cnt     := cnt + 1;
        if cnt = c_len then
          ser_end <= '1';
          cnt     := 0;
        end if;
      end if;
    end if;
  end process series_cnt;

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Member Data Documentation

average_cal division [Component Instantiation]

Division for average

Definition at line 177 of file statistics.vhd.

c_len integer := safe_div ( SERIES_LENGTH ) [Constant]

divisor

Definition at line 92 of file statistics.vhd.

division [Component]

Division.

Definition at line 57 of file statistics.vhd.

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The documentation for this class was generated from the following file:

• statistics.vhd