ddr2_data_buffer Entity Reference
Interface between DAQ & DDR2. More...
Inheritance diagram for ddr2_data_buffer:
Collaboration diagram for ddr2_data_buffer:
Architectures | |
| ddr2_data_buffer_arc | Architecture |
| Interface between DAQ & DDR2, buffer with circular addressing. More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| unisim | |
| Library with Xilinx primitives. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_arith | |
| arithmetic operations on std_logic datatypes, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
| numeric_std | |
| arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
| vcomponents | |
| Header with Xilinx primitives. | |
Ports | |
| CLKA | in std_logic |
| Clock read. | |
| CLKB | in std_logic |
| Clock write. | |
| RESET | in std_logic |
| Reset. | |
| WEN | in std_logic |
| Write Enable. | |
| REN | in std_logic |
| Read Enable. | |
| EMPTY | out std_logic |
| Empty flag. | |
| DATA_IN | in std_logic_vector ( 255 downto 0 ) |
| Data in. | |
| DATA_OUT | out std_logic_vector ( 127 downto 0 ) |
| Data out. | |
Detailed Description
Interface between DAQ & DDR2.Definition at line 39 of file ddr2_data_buffer.vhd.
Member Data Documentation
CLKA in std_logic [Port] |
CLKB in std_logic [Port] |
DATA_IN in std_logic_vector ( 255 downto 0 ) [Port] |
DATA_OUT out std_logic_vector ( 127 downto 0 ) [Port] |
EMPTY out std_logic [Port] |
ieee library [Library] |
standard IEEE library
Reimplemented in main_components.
Definition at line 24 of file ddr2_data_buffer.vhd.
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 32 of file ddr2_data_buffer.vhd.
REN in std_logic [Port] |
RESET in std_logic [Port] |
std_logic_1164 package [Package] |
std_logic definitions, see file
Reimplemented in main_components.
Definition at line 26 of file ddr2_data_buffer.vhd.
std_logic_arith package [Package] |
arithmetic operations on std_logic datatypes, see file
Definition at line 28 of file ddr2_data_buffer.vhd.
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 30 of file ddr2_data_buffer.vhd.
unisim library [Library] |
vcomponents package [Package] |
WEN in std_logic [Port] |
The documentation for this class was generated from the following file:
