ddr2_mem_rd_data_fifo_0 Entity Reference

DistRAM for read data. More...

Inheritance diagram for ddr2_mem_rd_data_fifo_0:

Collaboration diagram for ddr2_mem_rd_data_fifo_0:

List of all members.

Architectures

arc_rd_data_fifo Architecture

DistRAM for read data. More...

Libraries

ieee

standard IEEE library

work

unisim

Library with Xilinx primitives.

Packages

std_logic_1164

std_logic definitions, see file

std_logic_unsigned

unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file

numeric_std

arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file

ddr2_mem_parameters_0 Package <ddr2_mem_parameters_0>

vcomponents

Header with Xilinx primitives.

Ports

CLK in std_logic

RESET in std_logic

FIFO_RD_EN in std_logic

READ_EN_DELAYED_RISE in std_logic

READ_EN_DELAYED_Fall in std_logic

FIRST_RISING in std_logic

READ_DATA_RISE in std_logic_vector ( memory_width-1 downto 0 )

READ_DATA_Fall in std_logic_vector ( memory_width-1 downto 0 )

READ_DATA_FIFO_RISE out std_logic_vector ( memory_width-1 downto 0 )

READ_DATA_FIFO_Fall out std_logic_vector ( memory_width-1 downto 0 )

READ_DATA_VALID out std_logic

Detailed Description

DistRAM for read data.

This module instantiates the distributed RAM which stores the read data from the memory.

ieee library [Library]

standard IEEE library

numeric_std package [Package]

arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file

std_logic_1164 package [Package]

std_logic definitions, see file

std_logic_unsigned package [Package]

unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file

unisim library [Library]

Library with Xilinx primitives.

vcomponents package [Package]

Header with Xilinx primitives.

The documentation for this class was generated from the following file:


Architectures
arc_rd_data_fifo	Architecture
	DistRAM for read data. More...
Libraries
ieee
	standard IEEE library
work
unisim
	Library with Xilinx primitives.
Packages
std_logic_1164
	std_logic definitions, see file
std_logic_unsigned
	unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
numeric_std
	arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
ddr2_mem_parameters_0	Package <ddr2_mem_parameters_0>
vcomponents
	Header with Xilinx primitives.
Ports
CLK	in std_logic
RESET	in std_logic
FIFO_RD_EN	in std_logic
READ_EN_DELAYED_RISE	in std_logic
READ_EN_DELAYED_Fall	in std_logic
FIRST_RISING	in std_logic
READ_DATA_RISE	in std_logic_vector ( memory_width-1 downto 0 )
READ_DATA_Fall	in std_logic_vector ( memory_width-1 downto 0 )
READ_DATA_FIFO_RISE	out std_logic_vector ( memory_width-1 downto 0 )
READ_DATA_FIFO_Fall	out std_logic_vector ( memory_width-1 downto 0 )
READ_DATA_VALID	out std_logic