bcm_signal_delay Entity Reference
Flexible shift-register as delay unit. More...
Inheritance diagram for bcm_signal_delay:
Collaboration diagram for bcm_signal_delay:
Architectures | |
| bcm_signal_delay_arc | Architecture |
| runtime adjustable shift register, min delay = 8 clock cycles More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_arith | |
| arithmetic operations on std_logic datatypes, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
Ports | |
| CLK | in std_logic |
| 40 MHz clock | |
| SCLR | in std_logic |
| synchronous clear (reset) signal | |
| delay_setting | in std_logic_vector ( 7 downto 0 ) |
| delay length set | |
| data_input | in std_logic |
| input signal | |
| data_output | out std_logic |
| output signal | |
Attributes | |
| shreg_extract | string |
| shreg_extract | " yes " |
Detailed Description
Flexible shift-register as delay unit.Definition at line 33 of file bcm_signal_delay.vhd.
Member Data Documentation
CLK in std_logic [Port] |
data_input in std_logic [Port] |
data_output out std_logic [Port] |
delay_setting in std_logic_vector ( 7 downto 0 ) [Port] |
ieee library [Library] |
standard IEEE library
Reimplemented in main_components.
Definition at line 24 of file bcm_signal_delay.vhd.
SCLR in std_logic [Port] |
std_logic_1164 package [Package] |
std_logic definitions, see file
Reimplemented in main_components.
Definition at line 26 of file bcm_signal_delay.vhd.
std_logic_arith package [Package] |
arithmetic operations on std_logic datatypes, see file
Definition at line 28 of file bcm_signal_delay.vhd.
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 30 of file bcm_signal_delay.vhd.
The documentation for this class was generated from the following file:
