bcm_signal_delay.bcm_signal_delay_arc Architecture Reference
runtime adjustable shift register, min delay = 8 clock cycles More...
Inheritance diagram for bcm_signal_delay.bcm_signal_delay_arc:
Collaboration diagram for bcm_signal_delay.bcm_signal_delay_arc:
Processes | |
| signal_delay | ( CLK , SCLR ) |
Signals | |
| shift_register_0 | std_logic := ' 0 ' |
| shift_register_1 | std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' ) |
| shift_register_2 | std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' ) |
| shift_register_3 | std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' ) |
| shift_register_4 | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
| shift_register_5 | std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) |
| shift_register_6 | std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' ) |
| shift_register_7 | std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' ) |
| connection_0 | std_logic := ' 0 ' |
| connection_1 | std_logic := ' 0 ' |
| connection_2 | std_logic := ' 0 ' |
| connection_3 | std_logic := ' 0 ' |
| connection_4 | std_logic := ' 0 ' |
| connection_5 | std_logic := ' 0 ' |
| connection_6 | std_logic := ' 0 ' |
Detailed Description
runtime adjustable shift register, min delay = 8 clock cyclesDefinition at line 48 of file bcm_signal_delay.vhd.
Member Function Documentation
| signal_delay | ( CLK , | |
| SCLR ) |
8 shift registers, connected on the fly according to delay value min delay = 8 clock cycles
Definition at line 70 of file bcm_signal_delay.vhd.
00070 signal_delay : process (CLK, SCLR) 00071 begin 00072 if (SCLR = '1') then 00073 data_output <= '0'; 00074 shift_register_0 <= '0'; 00075 connection_0 <= '0'; 00076 connection_1 <= '0'; 00077 connection_2 <= '0'; 00078 connection_3 <= '0'; 00079 connection_4 <= '0'; 00080 connection_5 <= '0'; 00081 connection_6 <= '0'; 00082 elsif (CLK'event and CLK = '1') then 00083 if (delay_setting(0) = '1') then 00084 shift_register_0 <= data_input; 00085 connection_0 <= shift_register_0; 00086 else 00087 connection_0 <= data_input; 00088 end if; 00089 if (delay_setting(1) = '1') then 00090 shift_register_1 <= connection_0 & shift_register_1(1); 00091 connection_1 <= shift_register_1(0); 00092 else 00093 connection_1 <= connection_0; 00094 end if; 00095 if (delay_setting(2) = '1') then 00096 shift_register_2 <= connection_1 & shift_register_2(3 downto 1); 00097 connection_2 <= shift_register_2(0); 00098 else 00099 connection_2 <= connection_1; 00100 end if; 00101 if (delay_setting(3) = '1') then 00102 shift_register_3 <= connection_2 & shift_register_3(7 downto 1); 00103 connection_3 <= shift_register_3(0); 00104 else 00105 connection_3 <= connection_2; 00106 end if; 00107 if (delay_setting(4) = '1') then 00108 shift_register_4 <= connection_3 & shift_register_4(15 downto 1); 00109 connection_4 <= shift_register_4(0); 00110 else 00111 connection_4 <= connection_3; 00112 end if; 00113 if (delay_setting(5) = '1') then 00114 shift_register_5 <= connection_4 & shift_register_5(31 downto 1); 00115 connection_5 <= shift_register_5(0); 00116 else 00117 connection_5 <= connection_4; 00118 end if; 00119 if (delay_setting(6) = '1') then 00120 shift_register_6 <= connection_5 & shift_register_6(63 downto 1); 00121 connection_6 <= shift_register_6(0); 00122 else 00123 connection_6 <= connection_5; 00124 end if; 00125 if (delay_setting(7) = '1') then 00126 shift_register_7 <= connection_6 & shift_register_7(127 downto 1); 00127 data_output <= shift_register_7(0); 00128 else 00129 data_output <= connection_6; 00130 end if; 00131 end if; 00132 end process;
The documentation for this class was generated from the following file:
