eth_buf Entity Reference
Buffer between DDR2 and EMAC for clock domain crossing. More...
Inheritance diagram for eth_buf:
Collaboration diagram for eth_buf:
Architectures | |
| eth_buf_arc | Architecture |
| address generation for buffer More... | |
Libraries | |
| ieee | |
| standard IEEE library | |
| unisim | |
| Library with Xilinx primitives. | |
Packages | |
| std_logic_1164 | |
| std_logic definitions, see file | |
| std_logic_arith | |
| arithmetic operations on std_logic datatypes, see file | |
| std_logic_unsigned | |
| unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file | |
| numeric_std | |
| arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file | |
| vcomponents | |
| Header with Xilinx primitives. | |
Ports | |
| CLK_WR | in std_logic |
| Write clock. | |
| CLK_RD | in std_logic |
| Read clock. | |
| RES | in std_logic |
| Reset. | |
| RD | in std_logic |
| Read enable. | |
| WR | in std_logic |
| Write enable. | |
| DATA_IN | in std_logic_vector ( 127 downto 0 ) |
| Write data. | |
| DATA_OUT | out std_logic_vector ( 7 downto 0 ) |
| Read data. | |
Detailed Description
Buffer between DDR2 and EMAC for clock domain crossing.Definition at line 39 of file eth_buf.vhd.
Member Data Documentation
CLK_RD in std_logic [Port] |
CLK_WR in std_logic [Port] |
DATA_IN in std_logic_vector ( 127 downto 0 ) [Port] |
DATA_OUT out std_logic_vector ( 7 downto 0 ) [Port] |
ieee library [Library] |
numeric_std package [Package] |
arithmetic functions use ieee.numeric_std.all; operators for signed use ieee.numeric_std.all; unsigned datatypes, see file
Definition at line 32 of file eth_buf.vhd.
RD in std_logic [Port] |
RES in std_logic [Port] |
std_logic_1164 package [Package] |
std_logic definitions, see file
Reimplemented in main_components.
Definition at line 26 of file eth_buf.vhd.
std_logic_arith package [Package] |
std_logic_unsigned package [Package] |
unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file
Definition at line 30 of file eth_buf.vhd.
unisim library [Library] |
vcomponents package [Package] |
WR in std_logic [Port] |
The documentation for this class was generated from the following file:
