dss_comm Entity Reference

Interface to DSS (Detector Safety System) This entity provides two redundant signals to the DSS, 1 Warning and 1 Abort. Outputs are also settable from the outside. More...

Inheritance diagram for dss_comm:

Inheritance graph
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Collaboration diagram for dss_comm:

Collaboration graph
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List of all members.


Architectures

dss_comm_arc Architecture
 Interface to DSS (Detector Safety System) This entity provides the two redundant signals to the DSS. Outputs are settable from the outside. More...

Libraries

ieee 
 standard IEEE library

Packages

std_logic_1164 
 std_logic definitions, see file

Ports

CLK  in std_logic
 Clock.
RESET  in std_logic
 Reset.
SET  in std_logic_vector ( 1 downto 0 )
 Set Values, Bit 1 = Abort, Bit 0 = Warning.
SET_EN  in std_logic_vector ( 1 downto 0 )
 Set Enable.
DSS_ABORT_1  out std_logic
 Abort Out 1.
DSS_ABORT_2  out std_logic
 Abort Out 2.
DSS_WARNING_1  out std_logic
 Warning Out 1.
DSS_WARNING_2  out std_logic
 Warning Out 2.


Detailed Description

Interface to DSS (Detector Safety System) This entity provides two redundant signals to the DSS, 1 Warning and 1 Abort. Outputs are also settable from the outside.

Definition at line 33 of file dss_comm.vhd.


Member Data Documentation

CLK in std_logic [Port]

Clock.

Definition at line 36 of file dss_comm.vhd.

DSS_ABORT_1 out std_logic [Port]

Abort Out 1.

Definition at line 40 of file dss_comm.vhd.

DSS_ABORT_2 out std_logic [Port]

Abort Out 2.

Definition at line 41 of file dss_comm.vhd.

DSS_WARNING_1 out std_logic [Port]

Warning Out 1.

Definition at line 42 of file dss_comm.vhd.

DSS_WARNING_2 out std_logic [Port]

Warning Out 2.

Definition at line 43 of file dss_comm.vhd.

ieee library [Library]

standard IEEE library

Reimplemented in main_components.

Definition at line 25 of file dss_comm.vhd.

RESET in std_logic [Port]

Reset.

Definition at line 37 of file dss_comm.vhd.

SET in std_logic_vector ( 1 downto 0 ) [Port]

Set Values, Bit 1 = Abort, Bit 0 = Warning.

Definition at line 38 of file dss_comm.vhd.

SET_EN in std_logic_vector ( 1 downto 0 ) [Port]

Set Enable.

Definition at line 39 of file dss_comm.vhd.

std_logic_1164 package [Package]

std_logic definitions, see file

Reimplemented in main_components.

Definition at line 27 of file dss_comm.vhd.


The documentation for this class was generated from the following file:

Author: M.Niegl
Generated on Tue Nov 4 00:51:13 2008 for BCM-AAA by doxygen 1.5.7.1-20081012