bcm_rod_dp_updown_counter Entity Reference

Up-Down Counter. More...

Inheritance diagram for bcm_rod_dp_updown_counter:

Inheritance graph
[legend]
Collaboration diagram for bcm_rod_dp_updown_counter:

Collaboration graph
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List of all members.


Architectures

bcm_rod_dp_updown_counter_arc Architecture
 up-down counter More...

Libraries

ieee 
 standard IEEE library

Packages

std_logic_1164 
 std_logic definitions, see file
std_logic_arith 
 arithmetic operations on std_logic datatypes, see file
std_logic_unsigned 
 unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file

Ports

CLK  in std_logic
 40 MHz clock
CLK_2X  in std_logic
 80 MHz clock
SCLR  in std_logic
 synchronous clear (reset) signal
count_up  in std_logic
 80 MHz clocked count up flag
count_down  in std_logic
 40 MHz clocked count down flag
busy  out std_logic
 busy indicator signal
data_available  out std_logic
 output data valid indicator signal
write_error  out std_logic
 write data corruption error indicator signal
read_error  out std_logic
 read data corruption error indicator signal


Detailed Description

Up-Down Counter.

Dual speed (80 MHz count up and 40 MHz count down) up/down counter. "busy" is high if "dp_ram_updown_counter" is at highest count "data_available" is high if "dp_ram_updown_counter" is not a lowest count "write_error" is high if "count_up" during "dp_ram_updown_counter" is at highest count "read_error" is high if "count_down" during "dp_ram_updown_counter" is at lowest count

Definition at line 38 of file bcm_rod_dp_updown_counter.vhd.


Member Data Documentation

busy out std_logic [Port]

busy indicator signal

Definition at line 47 of file bcm_rod_dp_updown_counter.vhd.

CLK in std_logic [Port]

40 MHz clock

Definition at line 41 of file bcm_rod_dp_updown_counter.vhd.

CLK_2X in std_logic [Port]

80 MHz clock

Definition at line 42 of file bcm_rod_dp_updown_counter.vhd.

count_down in std_logic [Port]

40 MHz clocked count down flag

Definition at line 46 of file bcm_rod_dp_updown_counter.vhd.

count_up in std_logic [Port]

80 MHz clocked count up flag

Definition at line 45 of file bcm_rod_dp_updown_counter.vhd.

data_available out std_logic [Port]

output data valid indicator signal

Definition at line 48 of file bcm_rod_dp_updown_counter.vhd.

ieee library [Library]

standard IEEE library

Definition at line 24 of file bcm_rod_dp_updown_counter.vhd.

read_error out std_logic [Port]

read data corruption error indicator signal

Definition at line 50 of file bcm_rod_dp_updown_counter.vhd.

SCLR in std_logic [Port]

synchronous clear (reset) signal

Definition at line 43 of file bcm_rod_dp_updown_counter.vhd.

std_logic_1164 package [Package]

std_logic definitions, see file

Definition at line 26 of file bcm_rod_dp_updown_counter.vhd.

std_logic_arith package [Package]

arithmetic operations on std_logic datatypes, see file

Definition at line 28 of file bcm_rod_dp_updown_counter.vhd.

std_logic_unsigned package [Package]

unsigned functions use ieee.std_logic_unsigned.all; operators for std_logic_vector type, see file

Definition at line 30 of file bcm_rod_dp_updown_counter.vhd.

write_error out std_logic [Port]

write data corruption error indicator signal

Definition at line 49 of file bcm_rod_dp_updown_counter.vhd.


The documentation for this class was generated from the following file:

Author: M.Niegl
Generated on Tue Nov 4 00:48:46 2008 for BCM-AAA by doxygen 1.5.7.1-20081012