bcm_signal_delay_vec.bcm_signal_delay_vec_arc Architecture Reference

Flexible shift-register as delay unit. More...

Inheritance diagram for bcm_signal_delay_vec.bcm_signal_delay_vec_arc:

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Collaboration diagram for bcm_signal_delay_vec.bcm_signal_delay_vec_arc:

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List of all members.

Processes
wr_addr	( CLK , SCLR )
rd_addr	( CLK , SCLR )
Components
shift_reg	<Entity shift_reg>
	shift register built by BRAM blocks
Signals
rde	std_logic := ' 0 '
we	std_logic := ' 0 '
diff	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
addrb	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
addra	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
Component Instantiations
bram_shift_reg	shift_reg <Entity shift_reg>

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Detailed Description

Flexible shift-register as delay unit.

Definition at line 50 of file bcm_signal_delay_vec.vhd.

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Member Function Documentation

[Process]

wr_addr		( CLK ,
		SCLR )

purpose: generate cyclic write address type : sequential

Definition at line 76 of file bcm_signal_delay_vec.vhd.

  wr_addr : process (CLK, SCLR)
  begin  -- process wr_addr
    if SCLR = '1' then                  -- asynchronous reset (active high)
      addra <= (others => '0');
    elsif CLK'event and CLK = '1' then  -- rising clock edge
      addra <= addra + 1;
    end if;
  end process wr_addr;

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Member Data Documentation

shift_reg [Component]

shift register built by BRAM blocks

Definition at line 56 of file bcm_signal_delay_vec.vhd.

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The documentation for this class was generated from the following file:

• bcm_signal_delay_vec.vhd