bridge.bridge_arc Architecture Reference

top module of SATA More...

Inheritance diagram for bridge.bridge_arc:

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Collaboration diagram for bridge.bridge_arc:

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List of all members.

Processes
sen_imp_a	( CLK_SATA_IN )
	sending with "holes" = EOPs, ch A
sen_imp_b	( CLK_SATA_IN )
	sending with "holes" = EOPs, ch B
rec_imp_a	( CLK_SATA_IN )
	receiving with "holes" = EOPs, ch A
rec_imp_b	( CLK_SATA_IN )
	receiving with "holes" = EOPs, ch B
last_buf_a	( CLK_SATA_IN )
	assemble data of two cycles for output
last_buf_b	( CLK_SATA_IN )
	assemble data of two cycles for output
output_value_a	( CLK_DATA_IN )
	assemble data of two cycles for output
output_value_b	( CLK_DATA_IN )
	assemble data of two cycles for output
Components
sata	<Entity sata>
	SATA wrapper.
clock_divider	<Entity clock_divider>
	simple clock divider
Constants
cycle_limit	std_logic_vector ( 7 downto 0 ) := " 10000001 "
Types
states	( sending , eop , pause , receiving , skip )
Signals
state_a	states := sending
state_b	states := sending
state_II_a	states := receiving
state_II_b	states := receiving
a_txlock	std_logic
b_txlock	std_logic
a_rxlock	std_logic
b_rxlock	std_logic
t_a_ready	std_logic
t_b_ready	std_logic
r_a_ready	std_logic
r_b_ready	std_logic
phase_a	std_logic
phase_b	std_logic
counter_a	std_logic_vector ( 7 downto 0 )
counter_b	std_logic_vector ( 7 downto 0 )
counter_in_a	std_logic_vector ( 7 downto 0 )
counter_in_b	std_logic_vector ( 7 downto 0 )
sata_eop_a	std_logic
sata_eop_b	std_logic
sata_data_a	std_logic_vector ( 31 downto 0 )
sata_data_b	std_logic_vector ( 31 downto 0 )
data_direct_a	std_logic_vector ( 35 downto 0 )
data_direct_b	std_logic_vector ( 35 downto 0 )
data_delay_a	std_logic_vector ( 35 downto 0 )
data_delay_b	std_logic_vector ( 35 downto 0 )
sata_data_ready_a	std_logic
sata_data_ready_b	std_logic
sata_data_out_a	std_logic_vector ( 31 downto 0 )
sata_data_out_b	std_logic_vector ( 31 downto 0 )
sata_data_present_a	std_logic
sata_data_present_b	std_logic
sata_eop_signal_a	std_logic
sata_eop_signal_b	std_logic
p_good_a	std_logic
p_good_b	std_logic
p_bad_a	std_logic
p_bad_b	std_logic
package_report_a	std_logic
package_report_b	std_logic
last_buffer_a	std_logic_vector ( 65 downto 0 )
last_buffer_b	std_logic_vector ( 65 downto 0 )
sata_error_a	std_logic
sata_error_b	std_logic
delay_a	std_logic
delay_b	std_logic
Component Instantiations
sata_modul	sata <Entity sata>

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Detailed Description

top module of SATA

Definition at line 78 of file bridge.vhd.

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Member Function Documentation

[Process]

last_buf_a

( CLK_SATA_IN )

assemble data of two cycles for output

Definition at line 462 of file bridge.vhd.

  last_buf_a : process (CLK_SATA_IN)
  begin
    if CLK_SATA_IN'event and CLK_SATA_IN = '1' then
      if CLK_DATA_IN = '1' then
        last_buffer_a(31 downto 0) <= sata_data_out_a;
      else
        last_buffer_a(63 downto 32) <= sata_data_out_a;
        last_buffer_a(64)           <= sata_data_present_a;
        last_buffer_a(65)           <= sata_error_a;
      end if;
    end if;
  end process;

[Process]

last_buf_b

( CLK_SATA_IN )

assemble data of two cycles for output

Definition at line 476 of file bridge.vhd.

  last_buf_b : process (CLK_SATA_IN)
  begin
    if CLK_SATA_IN'event and CLK_SATA_IN = '1' then
      if CLK_DATA_IN = '1' then
        last_buffer_b(31 downto 0) <= sata_data_out_b;
      else
        last_buffer_b(63 downto 32) <= sata_data_out_b;
        last_buffer_b(64)           <= sata_data_present_b;
        last_buffer_b(65)           <= sata_error_b;
      end if;
    end if;
  end process;

[Process]

output_value_a

( CLK_DATA_IN )

assemble data of two cycles for output

Definition at line 490 of file bridge.vhd.

  output_value_a : process(CLK_DATA_IN)
  begin
    if CLK_DATA_IN'event and CLK_DATA_IN = '1' then
      A_DATA_OUT       <= last_buffer_a(63 downto 0);
      A_DATA_VALID_OUT <= last_buffer_a(64);
      A_DATA_ERROR     <= last_buffer_a(65);
    end if;
  end process;

[Process]

output_value_b

( CLK_DATA_IN )

assemble data of two cycles for output

Definition at line 500 of file bridge.vhd.

  output_value_b : process(CLK_DATA_IN)
  begin
    if CLK_DATA_IN'event and CLK_DATA_IN = '1' then
      B_DATA_OUT       <= last_buffer_b(63 downto 0);
      B_DATA_VALID_OUT <= last_buffer_b(64);
      B_DATA_ERROR     <= last_buffer_b(65);
    end if;
  end process;

[Process]

rec_imp_a

( CLK_SATA_IN )

receiving with "holes" = EOPs, ch A

Definition at line 361 of file bridge.vhd.

  rec_imp_a : process (CLK_SATA_IN)
  begin
    if CLK_SATA_IN'event and CLK_SATA_IN = '1' then
      if RESET_A_IN = '1' then
        --we are in the middle of reset
        counter_in_a <= (others => '0');
        state_II_a   <= receiving;
        delay_a      <= '0';
      else
        --normal running
        case state_II_a is
          when receiving =>
            if sata_eop_signal_a = '1' then
              state_II_a   <= eop;
              counter_in_a <= (others => '0');
              if CLK_DATA_IN = '0' then
                delay_a    <= not delay_a;
                state_II_a <= skip;
              end if;
            end if;
          when eop =>
            counter_in_a <= counter_in_a + 1;
            if counter_in_a = 2 then
              if package_report_a = '1' then
                p_good_a <= '1';
              else
                p_bad_a <= '1';
              end if;
            elsif counter_in_a = 4 then
              state_II_a   <= receiving;
              counter_in_a <= (others => '0');
              p_good_a     <= '0';
              p_bad_a      <= '0';
            end if;
            
          when skip =>
            state_II_a <= receiving;
            
          when others =>
            state_II_a   <= receiving;
            counter_in_a <= (others => '0');
            
        end case;
      end if;
    end if;
  end process;

[Process]

rec_imp_b

( CLK_SATA_IN )

receiving with "holes" = EOPs, ch B

Definition at line 409 of file bridge.vhd.

  rec_imp_b : process (CLK_SATA_IN)
  begin
    if CLK_SATA_IN'event and CLK_SATA_IN = '1' then
      if RESET_B_IN = '1' then
        --we are in the middle of reset
        counter_in_b <= (others => '0');
        state_II_b   <= receiving;
        delay_b      <= '0';
      else
        --normal running
        case state_II_b is
          when receiving =>
            if sata_eop_signal_b = '1' then
              state_II_b   <= eop;
              counter_in_b <= (others => '0');
              if CLK_DATA_IN = '0' then
                delay_b    <= not delay_b;
                state_II_b <= skip;
              end if;
            end if;
          when eop =>
            counter_in_b <= counter_in_b + 1;
            if counter_in_b = 2 then
              if package_report_b = '1' then
                p_good_b <= '1';
              else
                p_bad_b <= '1';
              end if;
            elsif counter_in_b = 4 then
              state_II_b   <= receiving;
              counter_in_b <= (others => '0');
              p_good_b     <= '0';
              p_bad_b      <= '0';
            end if;
            
          when skip =>
            state_II_b <= receiving;
            
          when others =>
            state_II_b   <= receiving;
            counter_in_b <= (others => '0');
            
        end case;
      end if;
    end if;
  end process;

[Process]

sen_imp_a

( CLK_SATA_IN )

sending with "holes" = EOPs, ch A

Definition at line 275 of file bridge.vhd.

  sen_imp_a : process (CLK_SATA_IN)
  begin
    if CLK_SATA_IN'event and CLK_SATA_IN = '1' then
      if RESET_A_IN = '1' then
        --we are in the middle of reset
        counter_a  <= (others => '0');
        phase_a    <= '0';
        state_a    <= sending;
        sata_eop_a <= '0';
      else
        --normal running
        phase_a <= not phase_a;
        case state_a is
          when sending =>
            counter_a <= counter_a + 1;
            if counter_a = cycle_limit then
              state_a    <= eop;
              counter_a  <= (others => '0');
              sata_eop_a <= '1';
            end if;
            
          when eop =>
            sata_eop_a <= '0';
            state_a    <= pause;
            
          when pause =>
            counter_a <= counter_a + 1;
            if counter_a = 2 then
              counter_a <= (others => '0');
              state_a   <= sending;
            end if;
            
          when others =>
            counter_a <= (others => '0');
            state_a   <= sending;
            
        end case;
        
      end if;
    end if;
  end process;

[Process]

sen_imp_b

( CLK_SATA_IN )

sending with "holes" = EOPs, ch B

Definition at line 318 of file bridge.vhd.

  sen_imp_b : process (CLK_SATA_IN)
  begin
    if CLK_SATA_IN'event and CLK_SATA_IN = '1' then
      if RESET_B_IN = '1' then
        --we are in the middle of reset
        counter_b  <= (others => '0');
        phase_b    <= '0';
        state_b    <= sending;
        sata_eop_b <= '0';
      else
        --normal running
        phase_b <= not phase_b;
        case state_b is
          when sending =>
            counter_b <= counter_b + 1;
            if counter_b = cycle_limit then
              state_b    <= eop;
              counter_b  <= (others => '0');
              sata_eop_b <= '1';
            end if;
            
          when eop =>
            sata_eop_b <= '0';
            state_b    <= pause;
            
          when pause =>
            counter_b <= counter_b + 1;
            if counter_b = 2 then
              counter_b <= (others => '0');
              state_b   <= sending;
            end if;
            
          when others =>
            counter_b <= (others => '0');
            state_b   <= sending;
            
        end case;
        
      end if;
    end if;
  end process;

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Member Data Documentation

clock_divider [Component]

simple clock divider

Definition at line 136 of file bridge.vhd.

sata [Component]

SATA wrapper.

Reimplemented in main_components.

Definition at line 81 of file bridge.vhd.

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The documentation for this class was generated from the following file:

• bridge.vhd