Here is a list of all documented class members with links to the class documentation for each member:

- s -

• S_ANDREJ1 : ctp_logic , delta_t_ac_top , intime
• S_ANDREJ1_O : intime
• S_ANDREJ2 : ctp_logic , delta_t_ac_top , intime
• S_ANDREJ2_O : intime
• S_EWA1 : ctp_logic , delta_t_ac_top , intime
• S_EWA1_O : intime
• S_EWA2 : ctp_logic , delta_t_ac_top , intime
• S_EWA2_O : intime
• S_HARRIS1 : ctp_logic , delta_t_ac_top , intime
• S_HARRIS1_O : intime
• S_HARRIS2 : ctp_logic , delta_t_ac_top , intime
• S_HARRIS2_O : intime
• S_HEINZ1 : ctp_logic , delta_t_ac_top , intime
• S_HEINZ1_O : intime
• S_HEINZ2 : ctp_logic , delta_t_ac_top , intime
• S_HEINZ2_O : intime
• S_HELMUT1 : ctp_logic , delta_t_ac_top , intime
• S_HELMUT1_O : intime
• S_HELMUT2 : ctp_logic , delta_t_ac_top , intime
• S_HELMUT2_O : intime
• S_IRENA1 : ctp_logic , delta_t_ac_top , intime
• S_IRENA1_O : intime
• S_IRENA2 : ctp_logic , delta_t_ac_top , intime
• S_IRENA2_O : intime
• S_LINK_END : command_decoder
• S_LINK_PAUSE : command_decoder
• S_LINK_START : command_decoder
• S_MARKO1 : ctp_logic , delta_t_ac_top , intime
• S_MARKO1_O : intime
• S_MARKO2 : ctp_logic , delta_t_ac_top , intime
• S_MARKO2_O : intime
• S_T1 : cal
• S_T2 : cal
• S_T3 : cal
• S_W1 : cal
• S_W2 : cal
• S_W3 : cal
• S_WILLIAM1 : ctp_logic , delta_t_ac_top , intime
• S_WILLIAM1_O : intime
• S_WILLIAM2 : ctp_logic , delta_t_ac_top , intime
• S_WILLIAM2_O : intime
• SA : comparator4
• safe_div() : division.division_arc , statistics.statistics_arc
• safe_implementation : rio2mem.rio2mem_arc
• sata : bridge.bridge_arc , main_components
• sata_cal_block_v1_4_1 : ROCKETIO_SATA.ROCKETIO_SATA_arc
• SATA_CLK : clocks
• sata_clk_i : clocks.coldplay
• SATA_LOGIC_CLK : clocks , rio2mem
• SATA_OK : rio2mem
• SATA_REF_CLK : rio2mem
• sata_wrapper : rio2mem.rio2mem_arc
• sataclkbuf : clocks.coldplay
• SB : comparator4
• SC : comparator4
• SCLR : bcm_rod , bcm_rod_dp_updown_counter , bcm_rod_formatter , bcm_rod_ram , bcm_rod_slink , bcm_rod_treadmil , bcm_signal_delay , bcm_signal_delay_vec
• SCOPE_OUT : sata
• SD : comparator4
• SEL_DONE : ddr2_mem_tap_logic_0
• select_for_each() : delta_t_ac_top.one_to_one
• sen_imp_a() : bridge.bridge_arc
• sen_imp_b() : bridge.bridge_arc
• SEND_ARP_ANN : rio2mem
• SEND_ERR_MSG : rio2mem
• SEND_PKT_SE : ethernet_top
• SEP_RES : side_4rios
• SEP_RESET : rios_all
• series_cnt() : statistics.statistics_arc
• SET : dss_comm
• SET_EN : ctp_comm , dss_comm
• set_second_active() : rio2mem.rio2mem_arc
• SET_SHIFT : daqrio_top , rio_rxtx
• SET_SHIFT_1 : side_4rios
• SET_SHIFT_2 : side_4rios
• set_tdaq_active() : rio2mem.rio2mem_arc
• SET_VAL : ctp_comm
• SF1 : bunchcycle
• SF2 : bunchcycle
• SF3 : bunchcycle
• SHA : auto_receiver , ncm_temac
• shift() : bcm_rod_treadmil.bcm_rod_treadmil_arc
• shift_clear_ddr() : rio2mem.rio2mem_arc
• shift_clear_ddr2() : rio2mem.rio2mem_arc
• shift_reg : bcm_signal_delay_vec.bcm_signal_delay_vec_arc
• shift_register_0 : GT11_INIT_RX.rtl , GT11_INIT_TX.rtl , sata_GT11_INIT_RX.rtl , sata_GT11_INIT_TX.rtl
• shift_register_1 : GT11_INIT_RX.rtl , GT11_INIT_TX.rtl , sata_GT11_INIT_RX.rtl , sata_GT11_INIT_TX.rtl
• shift_register_2 : GT11_INIT_RX.rtl , GT11_INIT_TX.rtl , sata_GT11_INIT_RX.rtl , sata_GT11_INIT_TX.rtl
• shift_register_3 : GT11_INIT_RX.rtl , GT11_INIT_TX.rtl , sata_GT11_INIT_RX.rtl , sata_GT11_INIT_TX.rtl
• side_4rios : main_components
• side_a : rios_all.rios_all_arc
• side_c : rios_all.rios_all_arc
• signal_delay() : bcm_signal_delay.bcm_signal_delay_arc
• SIGNAL_OUT : univibrator
• SIMULATION_P : RIO , ROCKETIO_SATA
• sl_end_force_extend : rio2mem.rio2mem_arc
• SL_LDOWN : bcm_aaa , rio2mem
• sl_ldown_i : rio2mem.rio2mem_arc
• SL_LFF : bcm_aaa , rio2mem
• sl_lff_i : rio2mem.rio2mem_arc
• SL_LRL : bcm_aaa , rio2mem
• SL_UCLK : bcm_aaa , rio2mem
• SL_UCTRL : bcm_aaa , rio2mem
• SL_UD : bcm_aaa , rio2mem
• SL_UDW : bcm_aaa , rio2mem
• SL_URESET : bcm_aaa , rio2mem
• SL_UTEST : bcm_aaa , rio2mem
• SL_UWEN : bcm_aaa , rio2mem
• SLINK_BEGIN_OF_FRAGMENT : bcm_rod_formatter
• slink_clock : bcm_rod_slink
• slink_control_word_flag : bcm_rod_slink
• slink_data_out : bcm_rod_slink
• slink_data_width : bcm_rod_slink
• SLINK_DOWN : tdaq_collector
• slink_down : bcm_rod_slink
• slink_down_FDRSE : bcm_rod_slink.bcm_rod_slink_arc
• SLINK_END_OF_FRAGMENT : bcm_rod_formatter
• slink_fsm() : bcm_rod_slink.bcm_rod_slink_arc
• SLINK_FULL : tdaq_collector
• slink_full_FDRSE : bcm_rod_slink.bcm_rod_slink_arc
• slink_full_flag : bcm_rod_slink
• slink_link_return_lines : bcm_rod_slink
• slink_reset : bcm_rod_slink
• slink_test : bcm_rod_slink
• slink_write_enable : bcm_rod_slink
• SOF : ncm_temac
• SOS_LED : bcm_aaa
• SOURCE_ID : command_decoder , tdaq_collector
• SOURCE_ID_PULSE : command_decoder
• SPA : auto_receiver , ncm_temac
• spike_suppress() : daq_header
• SR1 : bunchcycle
• SR2 : bunchcycle
• SR3 : bunchcycle
• src_IP_addr : udp_addresses
• src_MAC_1 : udp_addresses
• src_MAC_2 : udp_addresses
• src_port : udp_addresses
• SRL16E : GT11_INIT_RX.rtl , GT11_INIT_TX.rtl , sata_GT11_INIT_RX.rtl , sata_GT11_INIT_TX.rtl
• srst : l1a_fifo
• START : ethernet_top , status_collector , tdaq_collector
• start() : rio2mem.rio2mem_arc
• start_chksum : udp_addresses
• start_extend : rio2mem.rio2mem_arc
• START_INIT : GT11_INIT_RX , GT11_INIT_TX , sata_GT11_INIT_RX , sata_GT11_INIT_TX
• START_OF_RUN : command_decoder
• start_pkt_rsff() : rio2mem.rio2mem_arc
• start_pulse : status_collector.status_collector_arc , tdaq_collector.tdaq_collector_arc
• START_RUN : EVENT_cnt , ltp_comm , ORBIT_cnt
• start_run_extend : rio2mem.rio2mem_arc
• start_run_sync : rio2mem.rio2mem_arc
• STAT_F1 : cal
• STAT_F2 : cal
• STAT_F3 : cal
• stat_pkt_rsff() : rio2mem.rio2mem_arc
• STAT_R1 : cal
• STAT_R2 : cal
• STAT_R3 : cal
• STATE_MACHINE1 : ddr2_mem_parameters_0
• STATE_MACHINE2 : ddr2_mem_parameters_0
• statistics : main_components
• STATUS_CLK : status_collector , tdaq_collector
• status_collector : main_components
• STATUS_EF1 : bunchcycle
• STATUS_EF2 : bunchcycle
• STATUS_EF3 : bunchcycle
• STATUS_ER1 : bunchcycle
• STATUS_ER2 : bunchcycle
• STATUS_ER3 : bunchcycle
• STATUS_N1 : edge_det
• STATUS_N2 : edge_det
• STATUS_N3 : edge_det
• STATUS_P1 : edge_det
• STATUS_P2 : edge_det
• STATUS_P3 : edge_det
• STATUS_PKT : ethernet_top
• status_registers() : status_collector.status_collector_arc
• STATUS_T1_1 : daqrio_top
• STATUS_T1_2 : daqrio_top
• STATUS_T1_ANDREJ : side_4rios
• STATUS_T1_EWA : side_4rios
• STATUS_T1_HEINZ : side_4rios
• STATUS_T1_IRENA : side_4rios
• STATUS_T2_1 : daqrio_top
• STATUS_T2_2 : daqrio_top
• STATUS_T2_ANDREJ : side_4rios
• STATUS_T2_EWA : side_4rios
• STATUS_T2_HEINZ : side_4rios
• STATUS_T2_IRENA : side_4rios
• STATUS_T3_1 : daqrio_top
• STATUS_T3_2 : daqrio_top
• STATUS_T3_ANDREJ : side_4rios
• STATUS_T3_EWA : side_4rios
• STATUS_T3_HEINZ : side_4rios
• STATUS_T3_IRENA : side_4rios
• STATUS_W1_1 : daqrio_top
• STATUS_W1_2 : daqrio_top
• STATUS_W1_ANDREJ : side_4rios
• STATUS_W1_EWA : side_4rios
• STATUS_W1_HEINZ : side_4rios
• STATUS_W1_IRENA : side_4rios
• STATUS_W2_1 : daqrio_top
• STATUS_W2_2 : daqrio_top
• STATUS_W2_ANDREJ : side_4rios
• STATUS_W2_EWA : side_4rios
• STATUS_W2_HEINZ : side_4rios
• STATUS_W2_IRENA : side_4rios
• STATUS_W3_1 : daqrio_top
• STATUS_W3_2 : daqrio_top
• STATUS_W3_ANDREJ : side_4rios
• STATUS_W3_EWA : side_4rios
• STATUS_W3_HEINZ : side_4rios
• STATUS_W3_IRENA : side_4rios
• std_logic_1164 : ddr2_mem_top_0 , l1a_fifo , GT11_INIT_TX , ddr2_mem_rd_data_fifo_0 , EVENT_cnt , division , ddreth_buf , ddr2_mem_parameters_0 , ddr_chksum_adder , abort_buffer , abort_controller , ADDSUB48 , auto_receiver , bcm_aaa , bcm_emac_fifo , ddr2_mem_data_path_iobs_0 , bcm_emac_fifo_rx , bcm_rod , bcm_rod_dp_ram , ddr2_mem , bcm_rod_dp_updown_counter , bcm_rod_formatter , bcm_rod_ram , daq_header , bcm_rod_slink , bcm_rod_treadmil , bcm_signal_delay , bcm_signal_delay_vec , BID_cnt , bridge , buffer_3ST , bunchcycle , busy , cal , cal_block_v1_4_1 , cibu_comm , clock_divider , clocks , cnt_ddr2_rd , cnt_ddr_rd , command_decoder , comparator4 , ctp_comm , ctp_logic , daqrio_top , ddr2_chksum_cal , ddr2_data_buffer , ddr2_mem_backend_fifos_0 , ddr2_mem_controller_iobs_0 , ddr2_mem_data_path_0 , ddr2_mem_data_tap_inc , ddr2_mem_data_write_0 , ddr2_mem_ddr2_controller_0 , ddr2_mem_idelay_ctrl , ddr2_mem_infrastructure , ddr2_mem_infrastructure_iobs_0 , ddr2_mem_iobs_0 , ddr2_mem_pattern_compare8 , ddr2_mem_RAM_D_0 , ddr2_mem_rd_data_0 , ddr2_mem_rd_wr_addr_fifo_0 , ddr2_mem_tap_ctrl , ddr2_mem_tap_logic_0 , ddr2_mem_user_interface_0 , ddr2_mem_v4_dm_iob , ddr2_mem_v4_dq_iob , ddr2_mem_v4_dqs_iob , ddr2_mem_wr_data_fifo_16 , ddr2_usr_be , ddr_chksum_accu , ddr_chksum_cal , ddr_data_buffer , ddr_eth_buf , delay , delay_adj , delta_t_ac_top , dss_comm , edge , edge_det , edge_fal , eth_buf , ethbuf , ethernet_top , extend_test , generic_shift_reg , GT11_INIT_RX , incrementer , intime , ipmac , status_collector , LCD , lcd_characters , lcd_commander , lcd_controller , LFSR14_23A3 , loop_cnt , loop_cnt_sh , lvl1_buf , lvl1_circ_buffer , main_components , mem_interface_top_infrastructure , mem_interface_top_parameters_0 , MGT_CLOCK_MODULE , onescompaccu , onescomplementadder , ORBIT_cnt , period_check , pmdelay , prescaler , proc_data_emul , raw_buffer , raw_data_emul , RIO , rio_rxtx , riocheck , rios_all , sata , sata_cal_block_v1_4_1 , sata_GT11_INIT_RX , sata_GT11_INIT_TX , shift_reg , side_4rios , statistics , tdaq_collector , xtemac , temac_controller , udp_addresses , univibrator , timewindow , ltp_comm , ROCKETIO_SATA , rio2mem , ram_user_backend , ncm_temac , mem_interface_top_idelay_ctrl
• std_logic_arith : abort_controller , sata , delay_adj , ddr_eth_buf , edge_fal , ncm_temac , extend_test , LFSR14_23A3 , period_check , loop_cnt_sh , rio2mem , status_collector , univibrator , timewindow , ddr2_usr_be , riocheck , ORBIT_cnt , onescomplementadder , lcd_controller , lcd_commander , edge_det , edge , lvl1_buf , tdaq_collector , clock_divider , udp_addresses , rios_all , cal , daqrio_top , bcm_rod_slink , EVENT_cnt , ddr2_data_buffer , bcm_rod_ram , delay , auto_receiver , bcm_aaa , bcm_rod , ADDSUB48 , bcm_rod_dp_updown_counter , bcm_signal_delay , busy , BID_cnt , cnt_ddr2_rd , cnt_ddr_rd , command_decoder , ctp_logic , bcm_rod_treadmil , ddr_data_buffer , delta_t_ac_top , eth_buf , ethernet_top , LCD , bridge , loop_cnt , onescompaccu , bcm_rod_formatter , pmdelay , prescaler , ram_user_backend , rio_rxtx , clocks , side_4rios , bcm_signal_delay_vec , comparator4
• std_logic_unsigned : lcd_controller , rio_rxtx , delta_t_ac_top , delay_adj , onescomplementadder , univibrator , status_collector , ram_user_backend , ddr2_mem_iobs_0 , clocks , sata , tdaq_collector , comparator4 , edge , ddr2_mem , onescompaccu , ddr2_mem_RAM_D_0 , ddr2_mem_rd_data_fifo_0 , ddr2_mem_data_path_iobs_0 , LFSR14_23A3 , edge_fal , cnt_ddr_rd , ddr2_mem_parameters_0 , udp_addresses , timewindow , ethernet_top , bcm_rod_formatter , auto_receiver , cal , ddr_eth_buf , loop_cnt , extend_test , BID_cnt , side_4rios , ddr_data_buffer , ddr2_mem_rd_wr_addr_fifo_0 , bcm_rod_slink , riocheck , EVENT_cnt , bcm_rod_ram , rio2mem , loop_cnt_sh , abort_controller , ORBIT_cnt , prescaler , ADDSUB48 , ddr2_mem_data_write_0 , period_check , pmdelay , ddr2_mem_rd_data_0 , ddr2_mem_v4_dq_iob , lvl1_buf , ddr2_mem_controller_iobs_0 , ddr2_data_buffer , ddr2_mem_data_tap_inc , bcm_aaa , command_decoder , ddr2_mem_infrastructure_iobs_0 , rios_all , clock_divider , lcd_commander , edge_det , bunchcycle , bcm_rod_dp_updown_counter , bcm_rod_treadmil , ddr2_mem_data_path_0 , bridge , ddr2_mem_infrastructure , ddr2_mem_idelay_ctrl , ctp_logic , ddr2_mem_v4_dqs_iob , eth_buf , daqrio_top , delay , ddr2_mem_pattern_compare8 , cnt_ddr2_rd , bcm_signal_delay , ddr2_usr_be , bcm_rod , ddr2_mem_wr_data_fifo_16 , ddr2_mem_tap_ctrl , ddr2_mem_tap_logic_0 , bcm_signal_delay_vec , busy , LCD , ddr2_mem_user_interface_0 , ddr2_mem_v4_dm_iob , ddr2_mem_ddr2_controller_0 , ncm_temac , ddr2_mem_backend_fifos_0 , ddr2_mem_top_0
• std_port : udp_addresses
• stop : bcm_rod_ram , bcm_rod_treadmil
• STOP_PC : rio2mem
• StringToBool() : cal_block_v1_4_1.rtl
• STROBE : lcd_commander
• SUM_F_IN : bunchcycle
• SUM_F_OUT : bunchcycle
• SUM_FAL : edge_det
• SUM_FAL_1 : daqrio_top
• SUM_FAL_2 : daqrio_top
• SUM_FAL_ANDREJ : side_4rios
• SUM_FAL_EWA : side_4rios
• SUM_FAL_HEINZ : side_4rios
• SUM_FAL_IRENA : side_4rios
• SUM_FIN : cal
• SUM_FOUT : cal
• SUM_R_IN : bunchcycle
• SUM_R_OUT : bunchcycle
• SUM_RIN : cal
• SUM_RIS : edge_det
• SUM_RIS_1 : daqrio_top
• SUM_RIS_2 : daqrio_top
• SUM_RIS_ANDREJ : side_4rios
• SUM_RIS_EWA : side_4rios
• SUM_RIS_HEINZ : side_4rios
• SUM_RIS_IRENA : side_4rios
• SUM_ROUT : cal
• sums() : bunchcycle.bunchcycle_arc
• sw_to_err() : rio2mem.rio2mem_arc
• SY : comparator4
• SYNC : GT11_INIT_RX , GT11_INIT_TX , sata_GT11_INIT_RX , sata_GT11_INIT_TX
• sync_reset_in() : bcm_aaa.bcm_aaa_arc
• sync_wr_done : ddr2_chksum_cal.ddr2_dsp_chksum_cal_arc , ddr_chksum_cal.ddr_dsp_chksum_cal_arc
• sys_clk : temac_controller , ncm_temac
• SYS_CLK_N : mem_interface_top_infrastructure
• SYS_CLK_P : mem_interface_top_infrastructure
• SYS_RESET_IN : mem_interface_top_infrastructure , ram_user_backend
• sys_rst : ddr2_mem_top_0 , temac_controller , mem_interface_top_infrastructure
• sys_rst90 : ddr2_mem_top_0 , mem_interface_top_infrastructure
• sys_rst_ref_clk_1 : ddr2_mem_top_0 , mem_interface_top_infrastructure
• SYSCLK : ddr2_usr_be , bcm_aaa , ethernet_top , clocks
• SYSCLK_BUFFER : clocks.coldplay
• SYSCLK_INT : clocks
• SYSCLK_N : ram_user_backend
• SYSCLK_P : ram_user_backend