Here is a list of all documented class members with links to the class documentation for each member:

- r -

• R : prescaler
• R1 : bunchcycle
• R2 : bunchcycle
• R3 : bunchcycle
• R_W : ddr2_usr_be , ram_user_backend
• ram : bcm_rod.bcm_rod_arc
• RAM16X1D : ddr2_mem_RAM_D_0.arc_RAM
• RAM16X1D0 : ddr2_mem_RAM_D_0.arc_RAM
• RAM16X1D1 : ddr2_mem_RAM_D_0.arc_RAM
• RAM16X1D2 : ddr2_mem_RAM_D_0.arc_RAM
• RAM16X1D3 : ddr2_mem_RAM_D_0.arc_RAM
• RAM16X1D4 : ddr2_mem_RAM_D_0.arc_RAM
• RAM16X1D5 : ddr2_mem_RAM_D_0.arc_RAM
• RAM16X1D6 : ddr2_mem_RAM_D_0.arc_RAM
• RAM16X1D7 : ddr2_mem_RAM_D_0.arc_RAM
• ram_contr : ddr2_usr_be.ddr2_usr_be_arc
• RAM_controller : ram_user_backend.ram_user_backend_arc
• ram_fall0 : ddr2_mem_rd_data_fifo_0.arc_rd_data_fifo
• ram_fill_counter() : bcm_rod_dp_updown_counter.bcm_rod_dp_updown_counter_arc
• ram_input_address() : bcm_rod_ram.bcm_rod_ram_arc
• ram_output_address() : bcm_rod_ram.bcm_rod_ram_arc
• RAM_reader() : bcm_rod_formatter.bcm_rod_formatter_arc
• ram_rise0 : ddr2_mem_rd_data_fifo_0.arc_rd_data_fifo
• ram_user_backend : main_components
• rate_registers() : status_collector.status_collector_arc
• rate_reset_extend : rio2mem.rio2mem_arc
• RATES_CLK : status_collector
• raw_buffer : ddr2_data_buffer.ddr2_data_buffer_arc , rio2mem.rio2mem_arc
• RAW_DATA : rios_all
• RAW_DATA1 : daqrio_top
• RAW_DATA2 : daqrio_top
• RAW_DATA_ANDREJ : side_4rios
• raw_data_buffer : ddr2_data_buffer.ddr2_data_buffer_arc
• raw_data_emul : main_components
• RAW_DATA_EWA : side_4rios
• raw_data_gen : rio2mem.rio2mem_arc
• RAW_DATA_HEINZ : side_4rios
• RAW_DATA_IRENA : side_4rios
• raw_memory : rio2mem.rio2mem_arc
• raw_protocol : udp_addresses
• RD : ddr_eth_buf , eth_buf
• rd_addr() : ddr_eth_buf.ddr_eth_buf_arc , eth_buf.eth_buf_arc
• rd_addr_gen() : ddr2_data_buffer.ddr2_data_buffer_arc
• RD_BID : lvl1_buf
• rd_clk : bcm_emac_fifo , bcm_emac_fifo_rx
• rd_data_00 : ddr2_mem_user_interface_0.user_interface_arc
• rd_data_fall : ddr2_mem_pattern_compare8
• rd_data_fifo0 : ddr2_mem_rd_data_0.arc_rd_data
• rd_data_fifo1 : ddr2_mem_rd_data_0.arc_rd_data
• rd_data_fifo2 : ddr2_mem_rd_data_0.arc_rd_data
• rd_data_fifo3 : ddr2_mem_rd_data_0.arc_rd_data
• rd_data_fifo4 : ddr2_mem_rd_data_0.arc_rd_data
• rd_data_fifo5 : ddr2_mem_rd_data_0.arc_rd_data
• rd_data_fifo6 : ddr2_mem_rd_data_0.arc_rd_data
• rd_data_fifo7 : ddr2_mem_rd_data_0.arc_rd_data
• rd_data_rise : ddr2_mem_pattern_compare8
• rd_en : l1a_fifo , bcm_emac_fifo , bcm_emac_fifo_rx
• rd_en_fall : ddr2_mem_pattern_compare8
• rd_en_rise : ddr2_mem_pattern_compare8
• RD_OVER : ethernet_top
• rd_ovr_pat : udp_addresses
• rd_ovr_sync : rio2mem.rio2mem_arc
• rd_ram() : lvl1_buf.lvl1_buf_arc
• rd_rdy_pat : udp_addresses
• rd_rdy_sync : bcm_aaa.bcm_aaa_arc , ethernet_top.ethernet_top_arc , rio2mem.rio2mem_arc
• RD_READY : ethernet_top
• rd_wr_addr_fifo_00 : ddr2_mem_backend_fifos_0.arc_backend_fifos
• RDBURST_END : ddr2_usr_be , ram_user_backend
• rden_start() : temac_controller.temac_controller_arc
• rdy_chksum : udp_addresses
• rdy_pkt_indicator() : ethernet_top.ethernet_top_arc
• RDY_STATUS : ddr2_mem_idelay_ctrl , mem_interface_top_idelay_ctrl
• read_addr() : ddr_data_buffer.ddr_data_buffer_arc
• READ_DATA : ddr2_chksum_cal , ddr_chksum_cal
• READ_DATA_FALL : ddr2_mem_rd_data_0 , ddr2_mem_user_interface_0 , ddr2_mem_v4_dq_iob
• READ_DATA_FIFO_FALL : ddr2_mem_rd_data_0
• READ_DATA_FIFO_OUT : ddr2_mem_top_0 , ddr2_mem_user_interface_0
• READ_DATA_FIFO_RISE : ddr2_mem_rd_data_0
• READ_DATA_OUT : ram_user_backend
• READ_DATA_RISE : ddr2_mem_rd_data_0 , ddr2_mem_user_interface_0 , ddr2_mem_v4_dq_iob
• READ_DATA_VALID : ddr2_mem_rd_data_0 , ddr2_mem_top_0 , ddr2_mem_user_interface_0
• READ_DONE : rio2mem
• read_error : bcm_rod_dp_updown_counter , bcm_rod_ram
• READ_ERROR : lvl1_buf
• READ_OUT : incrementer , rio2mem
• read_out() : bunchcycle.bunchcycle_arc
• READ_OVER : rio2mem
• READ_OVER_extend : rio2mem.rio2mem_arc
• READ_READY : rio2mem
• READ_TDAQ_STATUS : command_decoder
• readout_controller_fsm() : rio2mem.rio2mem_arc
• readout_controller_proc() : rio2mem.rio2mem_arc
• readout_controller_raw() : rio2mem.rio2mem_arc
• READY : GT11_INIT_RX , GT11_INIT_TX , sata_GT11_INIT_RX , sata_GT11_INIT_TX
• realdatalen : udp_addresses
• rec_imp_a() : bridge.bridge_arc
• rec_imp_b() : bridge.bridge_arc
• REF : daqrio_top
• ref_clk : ddr2_mem_top_0
• REFCLK : clocks , rio_rxtx
• REFCLK1_OUT : MGT_CLOCK_MODULE
• REFCLK_N : rio2mem , clocks
• REFCLK_P : clocks , rio2mem
• REFCLKP_BUF : clocks.coldplay
• REFRESH_CLK : mem_interface_top_infrastructure
• refresh_clk : ddr2_mem_ddr2_controller_0
• reg_arr : generic_shift_reg.generic_shift_reg_arc
• registers_100() : tdaq_collector.tdaq_collector_arc
• registers_160() : tdaq_collector.tdaq_collector_arc
• registers_200() : tdaq_collector.tdaq_collector_arc
• registers_40() : tdaq_collector.tdaq_collector_arc
• REN : ddr2_data_buffer , ddr_data_buffer
• RES : abort_controller , busy , daqrio_top , ddr_eth_buf , delay , division , eth_buf , extend_test , generic_shift_reg , incrementer , onescompaccu , period_check , pmdelay , side_4rios , statistics
• RES_PC : rio2mem
• reserved : status_collector.status_collector_arc
• RESERVED : command_decoder
• RESET : bcm_aaa , BID_cnt , bunchcycle , cal_block_v1_4_1 , cibu_comm , clocks , cnt_ddr2_rd , cnt_ddr_rd , command_decoder , ctp_comm , ddr2_chksum_cal , ddr2_data_buffer , ddr2_mem_data_tap_inc , ddr2_mem_idelay_ctrl , ddr2_mem_rd_data_0 , ddr2_mem_user_interface_0 , ddr2_mem_v4_dq_iob , ddr2_mem_v4_dqs_iob , ddr_chksum_cal , ddr_data_buffer , dss_comm , ethernet_top , EVENT_cnt , loop_cnt , loop_cnt_sh , ltp_comm , lvl1_buf , mem_interface_top_idelay_ctrl , onescompaccu , onescomplementadder , ORBIT_cnt , proc_data_emul , raw_data_emul , rio2mem , rios_all , status_collector , tdaq_collector
• RESET0 : ddr2_mem_tap_logic_0
• RESET_A_IN : bridge
• RESET_B_IN : bridge
• RESET_CAL_CLK : ddr2_mem_tap_logic_0
• RESET_COUNTERS : command_decoder
• reset_ext : ddr2_usr_be.ddr2_usr_be_arc
• reset_extend : rio2mem.rio2mem_arc
• reset_force() : bcm_aaa.bcm_aaa_arc
• RESET_IN : ddr2_usr_be
• RESET_TB : ddr2_mem_top_0
• RESULT : ADDSUB48
• reverse4byte() : udp_addresses
• reverse_any_vector() : daq_header , udp_addresses
• rhigh_cnt() : abort_controller.abort_controller_arc
• rio : rio_rxtx.rio_rxtx_arc
• rio1 : rio_rxtx.rio_rxtx_arc
• rio2 : rio_rxtx.rio_rxtx_arc
• rio2mem : main_components
• RIO_CLK : status_collector , tdaq_collector
• RIO_DAQ : status_collector
• rio_or : main_components
• RIO_RESET : command_decoder
• rio_reset_extend : rio2mem.rio2mem_arc
• rio_rxtx : daqrio_top.daqrio_top_arc
• RIO_SATA : status_collector
• riocheck : main_components
• RIOCLK_1 : clocks , rio2mem , rios_all , side_4rios
• RIOCLK_2 : side_4rios , clocks , rio2mem , rios_all
• rioclkbuf : clocks.coldplay
• RIOERR : rio2mem
• RIOERR_TYPE : rio2mem
• rios2 : daqrio_top.daqrio_top_arc
• rios_all : main_components
• RIOS_READY : rio2mem , rios_all
• RIS1 : cal
• RIS2 : cal
• RIS3 : cal
• ris_hole_pattern() : daq_header
• ris_pattern() : daq_header
• rising_clock() : univibrator.univibrator_arc
• rlow_cnt() : abort_controller.abort_controller_arc
• ROCKETIO_SATA : sata.sata_arc
• rod : rio2mem.rio2mem_arc
• ROD_CLK : tdaq_collector
• rod_command_extend1 : rio2mem.rio2mem_arc
• rod_command_extend2 : rio2mem.rio2mem_arc
• rod_command_sync1 : rio2mem.rio2mem_arc
• rod_command_sync2 : rio2mem.rio2mem_arc
• rod_CTP_trigger_type : bcm_rod , bcm_rod_formatter
• rod_data_available : bcm_rod_formatter
• rod_data_next : bcm_rod_formatter
• rod_data_vld : bcm_rod_formatter
• rod_detector_event_type : bcm_rod , bcm_rod_formatter
• ROD_EMPTY : bcm_rod_formatter
• rod_format_version : bcm_rod , bcm_rod_formatter
• rod_fragment_end : bcm_rod_formatter
• ROD_HEADER : bcm_rod_formatter
• ROD_HEADER_WORDS : bcm_rod_formatter
• rod_input_data : bcm_rod_formatter
• rod_run_number : bcm_rod , bcm_rod_formatter
• rod_source_ID : bcm_rod_formatter , bcm_rod
• ROD_STATUS : status_collector
• ROD_STATUS_BLOCK_AFTER_DATA : bcm_rod_formatter
• ROD_STATUS_BLOCK_BEFORE_DATA : bcm_rod_formatter
• ROD_STATUS_BLOCK_WORD1 : bcm_rod_formatter
• ROD_STATUS_BLOCK_WORD2 : bcm_rod_formatter
• ROD_STATUS_BLOCK_WORDS : bcm_rod_formatter
• RS : lcd_controller , lcd_commander
• rst : bcm_emac_fifo , ddr2_mem_ddr2_controller_0
• RST : ADDSUB48
• rst : ddr2_mem_pattern_compare8 , bcm_emac_fifo_rx
• rst_n : ncm_temac
• RUN_NUMBER : tdaq_collector , command_decoder
• RUN_NUMBER_PULSE : command_decoder
• RW : lcd_commander , lcd_controller
• RX : ncm_temac.ncm_temac_arc
• RX1N_IN : daqrio_top
• RX1N_IN_1 : rio_rxtx
• RX1N_IN_2 : rio_rxtx
• RX1N_IN_AH : side_4rios
• RX1N_IN_IE : side_4rios
• RX1P_IN : daqrio_top
• RX1P_IN_1 : rio_rxtx
• RX1P_IN_2 : rio_rxtx
• RX1P_IN_AH : side_4rios
• RX1P_IN_IE : side_4rios
• RX_A_READY : sata , bridge
• RX_B_READY : sata , bridge
• rx_bad_packet : auto_receiver
• RX_DATA_OUT_1 : rio_rxtx
• RX_DATA_OUT_2 : rio_rxtx
• RX_FD_EN_P : RIO , ROCKETIO_SATA
• RX_FD_MIN_P : RIO , ROCKETIO_SATA
• RX_FD_WIDTH_P : RIO , ROCKETIO_SATA
• rx_fifo : temac_controller.temac_controller_arc
• rx_fifo_data : temac_controller , auto_receiver
• rx_fifo_en : auto_receiver
• rx_fifo_rden : temac_controller
• rx_fifo_rst : auto_receiver , temac_controller
• rx_good_packet : auto_receiver
• RX_LOCK : tdaq_collector
• RX_LOCK1 : rios_all
• RX_LOCK2 : rios_all
• RX_LOCK3 : rios_all
• RX_LOCK4 : rios_all
• RX_LOCK5 : rios_all
• RX_LOCK6 : rios_all
• RX_LOCK7 : rios_all
• RX_LOCK8 : rios_all
• rx_rderr : auto_receiver
• RX_READY : tdaq_collector
• RX_READY1 : rios_all
• RX_READY2 : rios_all
• RX_READY3 : rios_all
• RX_READY4 : rios_all
• RX_READY5 : rios_all
• RX_READY6 : rios_all
• RX_READY7 : rios_all
• RX_READY8 : rios_all
• RX_READY_FLAG : daqrio_top , rio_rxtx
• RX_READY_FLAG_AH : side_4rios
• RX_READY_FLAG_IE : side_4rios
• rx_res() : rio_rxtx.rio_rxtx_arc
• RX_SIGNAL_DETECT : cal_block_v1_4_1
• RX_SYSTEM_RESET_IN : rio_rxtx , daqrio_top , side_4rios
• rx_valid : auto_receiver
• RXDATA : ethernet_top
• RXDATAWIDTH_P : RIO.RIO_arc
• rxdest_port : udp_addresses
• rxdestip : udp_addresses
• RXINTDATAWIDTH_P : RIO.RIO_arc
• RXLOCK_OUT_ANDREJ : side_4rios
• RXLOCK_OUT_EWA : side_4rios
• RXLOCK_OUT_HEINZ : side_4rios
• RXLOCK_OUT_IRENA : side_4rios
• RXN_A_HH : rios_all , bcm_aaa , rio2mem
• RXN_A_WM : rio2mem , rios_all , bcm_aaa
• RXN_C_AH : rio2mem , rios_all , bcm_aaa
• RXN_C_IE : rio2mem , bcm_aaa , rios_all
• RXN_SATA_IN : bcm_aaa , sata , bridge , rio2mem
• RXP_A_HH : rio2mem , rios_all , bcm_aaa
• RXP_A_WM : rio2mem , bcm_aaa , rios_all
• RXP_C_AH : rios_all , bcm_aaa , rio2mem
• RXP_C_IE : rio2mem , bcm_aaa , rios_all
• RXP_SATA_IN : bridge , sata , bcm_aaa , rio2mem
• RXRECCLK1_OUT : rio_rxtx
• rxsrc_port : udp_addresses
• rxsrcip : udp_addresses
• RXVLD : ethernet_top