bridge.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/sata/bridge.vhd,v $
--*  $Revision: 1.1.2.5 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:49 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;


entity bridge is
  port(
    --CLOCKS-----------------------------------
    CLK_RIO_IN       : in  std_logic;
    CLK_DRP_IN       : in  std_logic;
    CLK_SATA_IN      : in  std_logic;
    USRCLK_STABLE_IN : in  std_logic;
    CLK_DATA_IN      : in  std_logic;
    --RESET------------------------------------
    RESET_A_IN       : in  std_logic;
    RESET_B_IN       : in  std_logic;
    --PACKAGE PINS-----------------------------
    RXP_SATA_IN      : in  std_logic_vector (1 downto 0);
    RXN_SATA_IN      : in  std_logic_vector (1 downto 0);
    TXP_SATA_OUT     : out std_logic_vector (1 downto 0);
    TXN_SATA_OUT     : out std_logic_vector (1 downto 0);
    --DIAGNOSTIC-------------------------------
    TX_A_READY       : out std_logic;
    TX_B_READY       : out std_logic;
    RX_A_READY       : out std_logic;
    RX_B_READY       : out std_logic;
    --DATA-------------------------------------
    A_DATA_IN        : in  std_logic_vector (63 downto 0);
    B_DATA_IN        : in  std_logic_vector (63 downto 0);
    A_DATA_VALID_IN  : in  std_logic;
    B_DATA_VALID_IN  : in  std_logic;
    A_DATA_OUT       : out std_logic_vector (63 downto 0);
    B_DATA_OUT       : out std_logic_vector (63 downto 0);
    A_DATA_VALID_OUT : out std_logic;
    B_DATA_VALID_OUT : out std_logic;
    A_DATA_ERROR     : out std_logic;
    B_DATA_ERROR     : out std_logic;
    A_LISTENING      : out std_logic;
    B_LISTENING      : out std_logic;
    --PACKAGE----------------------------------
    A_PACKAGE_GOOD   : out std_logic;
    B_PACKAGE_GOOD   : out std_logic;
    A_PACKAGE_BAD    : out std_logic;
    B_PACKAGE_BAD    : out std_logic;
    --SCOPE------------------------------------
    c_scope          : out std_logic_vector (165 downto 0)
    );
end bridge;


architecture bridge_arc of bridge is


  component sata is
    generic (
      C_SIMULATION : integer := 0       -- Set to 1 for simulation
      );
    port
      (
        --CLOCK-PORTS---------------------------------------------------------------------
        CLK_RIO_IN           : in  std_logic;  --RIOs reference clock
        CLK_DRP_IN           : in  std_logic;  --50MHz system clock for PLL correction (used) and DRP (nou used), used also for reset clocking since it is slover than TXOUTCLK1/2 = 75 MHz
        CLK_DATA_IN          : in  std_logic;  --clock for data Retrieval 
        USRCLK_STABLE_IN     : in  std_logic;  --stable then '1' --signaling stable inputs of input clocks
        --RESET-PORTS---------------------------------------------------------------------
        TX_A_SYSTEM_RESET_IN : in  std_logic;  --reset signal for both TX
        TX_B_SYSTEM_RESET_IN : in  std_logic;  --reset signal for both TX
        --PACKAGE-PINS--------------------------------------------------------------------
        RXP_SATA_IN          : in  std_logic_vector (1 downto 0);  --package pins
        RXN_SATA_IN          : in  std_logic_vector (1 downto 0);  --package pins
        TXP_SATA_OUT         : out std_logic_vector (1 downto 0);  --package pins
        TXN_SATA_OUT         : out std_logic_vector (1 downto 0);  --package pins
        --STATUS-PORTS--------------------------------------------------------------------
        MGTA_TXLOCK_OUT      : out std_logic;  --PLL lock state
        MGTA_RXLOCK_OUT      : out std_logic;  --PLL lock state
        MGTB_TXLOCK_OUT      : out std_logic;  --PLL lock state
        MGTB_RXLOCK_OUT      : out std_logic;  --PLL lock state
        TX_A_READY           : out std_logic;  --transmitrers ready
        RX_A_READY           : out std_logic;  --receivers ready
        TX_B_READY           : out std_logic;  --transmitrers ready
        RX_B_READY           : out std_logic;  --receivers ready
        --DATA-PORTS----------------------------------------------------------------------
        A_DATA_IN            : in  std_logic_vector (31 downto 0);  --data to be send
        B_DATA_IN            : in  std_logic_vector (31 downto 0);  --data to be send
        A_DATA_CONTROL_IN    : in  std_logic_vector (3 downto 0);  --'1' bits encodes coresponding byte as comma character
        B_DATA_CONTROL_IN    : in  std_logic_vector (3 downto 0);  --'1' bits encodes coresponding byte as comma character
        A_DATA_READY_IN      : in  std_logic;  --'1' if data is to be sent '0' if there is no data
        B_DATA_READY_IN      : in  std_logic;  --'1' if data is to be sent '0' if there is no data
        A_EOP_IN             : in  std_logic;  --initiate the end of package sequence --must be only one CLK_DATA_IN cycle long
        B_EOP_IN             : in  std_logic;  --initiate the end of package sequence --must be only one CLK_DATA_IN cycle long
        A_DATA_OUT           : out std_logic_vector (31 downto 0);  --data received
        B_DATA_OUT           : out std_logic_vector (31 downto 0);  --data received
        A_DATA_READY_OUT     : out std_logic;  --'1' if received data is avalible, '0' if there is no data
        B_DATA_READY_OUT     : out std_logic;  --'1' if received data is avalible, '0' if there is no data
        A_DATA_CONTROL_OUT   : out std_logic_vector (3 downto 0);  --'1' bit coresponds to byte as comma character
        B_DATA_CONTROL_OUT   : out std_logic_vector (3 downto 0);  --'1' bit coresponds to byte as comma character
        A_EOP_OUT            : out std_logic;  --signals, that end of package has been received
        B_EOP_OUT            : out std_logic;  --signals, that end of package has been received
        A_PACKAGE_OK_OUT     : out std_logic;  --four CLK_DATA_IN cycles lather than EOP_OUT this signal indicates whether previous packet was received correctly
        B_PACKAGE_OK_OUT     : out std_logic;  --four CLK_DATA_IN cycles lather than EOP_OUT this signal indicates whether previous packet was received correctly
        A_DATA_ERROR_OUT     : out std_logic;  --'1' if error ocoured, '0' if ok
        B_DATA_ERROR_OUT     : out std_logic;  --'1' if error ocoured, '0' if ok
        --CHIPSCOPE-PORTS-----------------------------------------------------------------
        SCOPE_OUT            : out std_logic_vector (191 downto 0)
        );
  end component;


  component clock_divider is
    generic(
      DIVISION_FACTOR : integer := 2;   --only even numbers
      INITIAL_VALUE   : integer := 2    --only even numbers
      );
    port(
      CLK_IN  : in  std_logic;
      CLK_OUT : out std_logic
      );
  end component;

  --signals----------------------------------------------------------------
  constant cycle_limit         : std_logic_vector(7 downto 0) := "10000001";  --must be in a form of 2n+1
  type     states is (sending, eop, pause, receiving, skip);
  signal   state_a             : states                       := sending;
  signal   state_b             : states                       := sending;
  signal   state_II_a          : states                       := receiving;
  signal   state_II_b          : states                       := receiving;
  signal   a_txlock            : std_logic;
  signal   b_txlock            : std_logic;
  signal   a_rxlock            : std_logic;
  signal   b_rxlock            : std_logic;
  signal   t_a_ready           : std_logic;
  signal   t_b_ready           : std_logic;
  signal   r_a_ready           : std_logic;
  signal   r_b_ready           : std_logic;
  signal   phase_a             : std_logic;
  signal   phase_b             : std_logic;
  signal   counter_a           : std_logic_vector (7 downto 0);
  signal   counter_b           : std_logic_vector (7 downto 0);
  signal   counter_in_a        : std_logic_vector (7 downto 0);
  signal   counter_in_b        : std_logic_vector (7 downto 0);
  signal   sata_eop_a          : std_logic;
  signal   sata_eop_b          : std_logic;
  signal   sata_data_a         : std_logic_vector (31 downto 0);
  signal   sata_data_b         : std_logic_vector (31 downto 0);
  signal   data_direct_a       : std_logic_vector (35 downto 0);
  signal   data_direct_b       : std_logic_vector (35 downto 0);
  signal   data_delay_a        : std_logic_vector (35 downto 0);
  signal   data_delay_b        : std_logic_vector (35 downto 0);
  signal   sata_data_ready_a   : std_logic;
  signal   sata_data_ready_b   : std_logic;
  signal   sata_data_out_a     : std_logic_vector (31 downto 0);
  signal   sata_data_out_b     : std_logic_vector (31 downto 0);
  signal   sata_data_present_a : std_logic;
  signal   sata_data_present_b : std_logic;
  signal   sata_eop_signal_a   : std_logic;
  signal   sata_eop_signal_b   : std_logic;
  signal   p_good_a            : std_logic;
  signal   p_good_b            : std_logic;
  signal   p_bad_a             : std_logic;
  signal   p_bad_b             : std_logic;
  signal   package_report_a    : std_logic;
  signal   package_report_b    : std_logic;
  signal   last_buffer_a       : std_logic_vector(65 downto 0);
  signal   last_buffer_b       : std_logic_vector(65 downto 0);
  signal   sata_error_a        : std_logic;
  signal   sata_error_b        : std_logic;
  signal   delay_a             : std_logic;
  signal   delay_b             : std_logic;
  
begin

  sata_modul : sata port map(
    --CLOCK-PORTS---------------------------------------------------------------------
    CLK_RIO_IN           => CLK_RIO_IN,
    CLK_DRP_IN           => CLK_DRP_IN,
    CLK_DATA_IN          => CLK_SATA_IN,
    USRCLK_STABLE_IN     => USRCLK_STABLE_IN,
    --RESET-PORTS---------------------------------------------------------------------
    TX_A_SYSTEM_RESET_IN => RESET_A_IN,
    TX_B_SYSTEM_RESET_IN => RESET_B_IN,
    --PACKAGE-PINS--------------------------------------------------------------------
    RXP_SATA_IN          => RXP_SATA_IN,
    RXN_SATA_IN          => RXN_SATA_IN,
    TXP_SATA_OUT         => TXP_SATA_OUT,
    TXN_SATA_OUT         => TXN_SATA_OUT,
    --STATUS-PORTS--------------------------------------------------------------------
    MGTA_TXLOCK_OUT      => a_txlock,
    MGTA_RXLOCK_OUT      => a_rxlock,
    MGTB_TXLOCK_OUT      => b_txlock,
    MGTB_RXLOCK_OUT      => b_rxlock,
    TX_A_READY           => t_a_ready,
    RX_A_READY           => r_a_ready,
    TX_B_READY           => t_b_ready,
    RX_B_READY           => r_b_ready,
    --DATA-PORTS----------------------------------------------------------------------
    A_DATA_IN            => sata_data_a,
    B_DATA_IN            => sata_data_b,
    A_DATA_CONTROL_IN     => "0000",
    B_DATA_CONTROL_IN    => "0000" ,
    A_DATA_READY_IN      => sata_data_ready_a ,
    B_DATA_READY_IN      => sata_data_ready_b ,
    A_EOP_IN             => sata_eop_a,
    B_EOP_IN              => sata_eop_b,
    A_DATA_OUT            => data_direct_a(31 downto 0),
    B_DATA_OUT           => data_direct_b(31 downto 0),
    A_DATA_READY_OUT     => data_direct_a(33),
    B_DATA_READY_OUT     => data_direct_b(33),
    A_DATA_CONTROL_OUT   => open,
    B_DATA_CONTROL_OUT   => open,
    A_EOP_OUT            => data_direct_a(32),
    B_EOP_OUT            => data_direct_b(32),
    A_PACKAGE_OK_OUT     => data_direct_a(34),
    B_PACKAGE_OK_OUT     => data_direct_b(34),
    A_DATA_ERROR_OUT     => data_direct_a(35),
    B_DATA_ERROR_OUT     => data_direct_b(35),
    --CHIPSCOPE-PORTS-----------------------------------------------------------------
    SCOPE_OUT            => open
    );

  --delay line
  data_delay_a <= data_direct_a when rising_edge(CLK_SATA_IN);
  data_delay_b <= data_direct_b when rising_edge(CLK_SATA_IN);

  --delay or not
  sata_data_out_a     <= data_direct_a(31 downto 0) when delay_a = '0'                                 else data_delay_a(31 downto 0);
  sata_data_out_b     <= data_direct_b(31 downto 0) when delay_b = '0'                                 else data_delay_b(31 downto 0);
  sata_eop_signal_a   <= data_direct_a(32)          when delay_a = '0'                                 else data_delay_a(32);
  sata_eop_signal_b   <= data_direct_b(32)          when delay_b = '0'                                 else data_delay_b(32);
  sata_data_present_a <= data_direct_a(33)          when delay_a = '0'                                 else data_delay_a(33);
  sata_data_present_b <= data_direct_b(33)          when delay_b = '0'                                 else data_delay_b(33);
  package_report_a    <= data_direct_a(34)          when delay_a = '0'                                 else data_delay_a(34);
  package_report_b    <= data_direct_b(34)          when delay_b = '0'                                 else data_delay_b(34);
  sata_error_a        <= data_direct_a(35)          when delay_a = '0'                                 else data_delay_a(35);
  sata_error_b        <= data_direct_b(35)          when delay_b = '0'                                 else data_delay_b(35);
  A_LISTENING         <= '1'                        when (state_a = sending and RESET_A_IN = '0')      else '0';
  B_LISTENING         <= '1'                        when (state_b = sending and RESET_B_IN = '0')      else '0';
  sata_data_ready_a   <= '1'                        when (state_a = sending and A_DATA_VALID_IN = '1') else '0';
  sata_data_ready_b   <= '1'                        when (state_b = sending and B_DATA_VALID_IN = '1') else '0';
  sata_data_a         <= A_DATA_IN(31 downto 0)     when (phase_a = '0')                               else A_DATA_IN(63 downto 32);
  sata_data_b         <= B_DATA_IN(31 downto 0)     when (phase_b = '0')                               else B_DATA_IN(63 downto 32);

  TX_A_READY <= t_a_ready and a_txlock;
  TX_B_READY <= t_b_ready and b_txlock;
  RX_A_READY <= r_a_ready and a_rxlock;
  RX_B_READY <= r_b_ready and b_rxlock;


  sen_imp_a : process (CLK_SATA_IN)
  begin
    if CLK_SATA_IN'event and CLK_SATA_IN = '1' then
      if RESET_A_IN = '1' then
        --we are in the middle of reset
        counter_a  <= (others => '0');
        phase_a    <= '0';
        state_a    <= sending;
        sata_eop_a <= '0';
      else
        --normal running
        phase_a <= not phase_a;
        case state_a is
          when sending =>
            counter_a <= counter_a + 1;
            if counter_a = cycle_limit then
              state_a    <= eop;
              counter_a  <= (others => '0');
              sata_eop_a <= '1';
            end if;
            
          when eop =>
            sata_eop_a <= '0';
            state_a    <= pause;
            
          when pause =>
            counter_a <= counter_a + 1;
            if counter_a = 2 then
              counter_a <= (others => '0');
              state_a   <= sending;
            end if;
            
          when others =>
            counter_a <= (others => '0');
            state_a   <= sending;
            
        end case;
        
      end if;
    end if;
  end process;


  sen_imp_b : process (CLK_SATA_IN)
  begin
    if CLK_SATA_IN'event and CLK_SATA_IN = '1' then
      if RESET_B_IN = '1' then
        --we are in the middle of reset
        counter_b  <= (others => '0');
        phase_b    <= '0';
        state_b    <= sending;
        sata_eop_b <= '0';
      else
        --normal running
        phase_b <= not phase_b;
        case state_b is
          when sending =>
            counter_b <= counter_b + 1;
            if counter_b = cycle_limit then
              state_b    <= eop;
              counter_b  <= (others => '0');
              sata_eop_b <= '1';
            end if;
            
          when eop =>
            sata_eop_b <= '0';
            state_b    <= pause;
            
          when pause =>
            counter_b <= counter_b + 1;
            if counter_b = 2 then
              counter_b <= (others => '0');
              state_b   <= sending;
            end if;
            
          when others =>
            counter_b <= (others => '0');
            state_b   <= sending;
            
        end case;
        
      end if;
    end if;
  end process;


  rec_imp_a : process (CLK_SATA_IN)
  begin
    if CLK_SATA_IN'event and CLK_SATA_IN = '1' then
      if RESET_A_IN = '1' then
        --we are in the middle of reset
        counter_in_a <= (others => '0');
        state_II_a   <= receiving;
        delay_a      <= '0';
      else
        --normal running
        case state_II_a is
          when receiving =>
            if sata_eop_signal_a = '1' then
              state_II_a   <= eop;
              counter_in_a <= (others => '0');
              if CLK_DATA_IN = '0' then
                delay_a    <= not delay_a;
                state_II_a <= skip;
              end if;
            end if;
          when eop =>
            counter_in_a <= counter_in_a + 1;
            if counter_in_a = 2 then
              if package_report_a = '1' then
                p_good_a <= '1';
              else
                p_bad_a <= '1';
              end if;
            elsif counter_in_a = 4 then
              state_II_a   <= receiving;
              counter_in_a <= (others => '0');
              p_good_a     <= '0';
              p_bad_a      <= '0';
            end if;
            
          when skip =>
            state_II_a <= receiving;
            
          when others =>
            state_II_a   <= receiving;
            counter_in_a <= (others => '0');
            
        end case;
      end if;
    end if;
  end process;


  rec_imp_b : process (CLK_SATA_IN)
  begin
    if CLK_SATA_IN'event and CLK_SATA_IN = '1' then
      if RESET_B_IN = '1' then
        --we are in the middle of reset
        counter_in_b <= (others => '0');
        state_II_b   <= receiving;
        delay_b      <= '0';
      else
        --normal running
        case state_II_b is
          when receiving =>
            if sata_eop_signal_b = '1' then
              state_II_b   <= eop;
              counter_in_b <= (others => '0');
              if CLK_DATA_IN = '0' then
                delay_b    <= not delay_b;
                state_II_b <= skip;
              end if;
            end if;
          when eop =>
            counter_in_b <= counter_in_b + 1;
            if counter_in_b = 2 then
              if package_report_b = '1' then
                p_good_b <= '1';
              else
                p_bad_b <= '1';
              end if;
            elsif counter_in_b = 4 then
              state_II_b   <= receiving;
              counter_in_b <= (others => '0');
              p_good_b     <= '0';
              p_bad_b      <= '0';
            end if;
            
          when skip =>
            state_II_b <= receiving;
            
          when others =>
            state_II_b   <= receiving;
            counter_in_b <= (others => '0');
            
        end case;
      end if;
    end if;
  end process;

  A_PACKAGE_GOOD <= p_good_a;
  B_PACKAGE_GOOD <= p_good_b;
  A_PACKAGE_BAD  <= p_bad_a;
  B_PACKAGE_BAD  <= p_bad_b;


  last_buf_a : process (CLK_SATA_IN)
  begin
    if CLK_SATA_IN'event and CLK_SATA_IN = '1' then
      if CLK_DATA_IN = '1' then
        last_buffer_a(31 downto 0) <= sata_data_out_a;
      else
        last_buffer_a(63 downto 32) <= sata_data_out_a;
        last_buffer_a(64)           <= sata_data_present_a;
        last_buffer_a(65)           <= sata_error_a;
      end if;
    end if;
  end process;


  last_buf_b : process (CLK_SATA_IN)
  begin
    if CLK_SATA_IN'event and CLK_SATA_IN = '1' then
      if CLK_DATA_IN = '1' then
        last_buffer_b(31 downto 0) <= sata_data_out_b;
      else
        last_buffer_b(63 downto 32) <= sata_data_out_b;
        last_buffer_b(64)           <= sata_data_present_b;
        last_buffer_b(65)           <= sata_error_b;
      end if;
    end if;
  end process;


  output_value_a : process(CLK_DATA_IN)
  begin
    if CLK_DATA_IN'event and CLK_DATA_IN = '1' then
      A_DATA_OUT       <= last_buffer_a(63 downto 0);
      A_DATA_VALID_OUT <= last_buffer_a(64);
      A_DATA_ERROR     <= last_buffer_a(65);
    end if;
  end process;


  output_value_b : process(CLK_DATA_IN)
  begin
    if CLK_DATA_IN'event and CLK_DATA_IN = '1' then
      B_DATA_OUT       <= last_buffer_b(63 downto 0);
      B_DATA_VALID_OUT <= last_buffer_b(64);
      B_DATA_ERROR     <= last_buffer_b(65);
    end if;
  end process;

  c_scope <= (others => '0');

end bridge_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:02 2008 for BCM-AAA by  1.5.7.1-20081012