ddr2_mem_infrastructure.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr2/ddr2_mem_infrastructure.vhd,v $
--*  $Revision: 1.5.2.4 $                                      *
--*  $Name: dev $                                              *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 21:55:53 $                              *


--*                                                            *
--**************************************************************
-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  / Vendor: Xilinx
-- \   \   \/ Version: 1.6
--  \   \ Application : MIG
--  /   / Filename: ddr2_mem_infrastructure.vhd
-- /___/   /\ Date Last Modified:  Wed Jun 1 2005
-- \   \  /  \Date Created: Mon May 2 2005
--  \___\/\___\
-- 
-- Device: Virtex-4
-- Design Name: DDR2_V4
-------------------------------------------------------------------------------


library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

library unisim;

use unisim.vcomponents.all;






entity ddr2_mem_infrastructure is
  port (
    SYS_RESET_IN      : in  std_logic;
    SYS_CLK_P         : in  std_logic;
    SYS_CLK_N         : in  std_logic;
    CLK200_P          : in  std_logic;
    CLK200_N          : in  std_logic;
    LOCK              : in  std_logic;
    CLK               : out std_logic;
    CLK90             : out std_logic;
    CLK50             : out std_logic;
    CLK200            : out std_logic;
    REFRESH_CLK       : out std_logic;
    sys_rst           : out std_logic;
    sys_rst90         : out std_logic;
    sys_rst_ref_clk_1 : out std_logic
    );

end entity;






architecture arc_infrastructure of ddr2_mem_infrastructure is


  component BUFG
    port(
      O : out std_ulogic;
      I : in  std_ulogic
      );
  end component;

  signal clk0_bufg_in       : std_logic;
  signal clk90_bufg_in      : std_logic;
  signal clkdv_bufg_in      : std_logic;
  signal clk50_bufg_in      : std_logic;
  signal clk0_bufg_out      : std_logic;
  signal clk90_bufg_out     : std_logic;
  signal clkdv_bufg_out     : std_logic;
  signal clk50_bufg_out     : std_logic;
  signal dcm_lock           : std_logic;
  signal dcm_lock_res       : std_logic;
  signal sys_rst_0          : std_logic;
  signal sys_rst_1          : std_logic;
  signal sys_rst_2          : std_logic;
  signal sys_rst_3          : std_logic;
  signal sys_rst90_0        : std_logic;
  signal sys_rst90_1        : std_logic;
  signal sys_rst90_2        : std_logic;
  signal sys_rst90_3        : std_logic;
  signal sys_rst_ref_clk_0  : std_logic;
  signal sys_rst_ref_clk    : std_logic;
  signal sys_rst_ref_clk_1r : std_logic;
  signal SYS_RESET          : std_logic;

begin

  sys_rst_ref_clk_1 <= sys_rst_ref_clk_1r;
  SYS_RESET         <= not SYS_RESET_IN;
  CLK               <= clk0_bufg_out;
  CLK90             <= clk90_bufg_out;
  CLK200            <= clk0_bufg_out;
  REFRESH_CLK       <= clkdv_bufg_out;
  CLK50             <= clk50_bufg_out;
  dcm_lock_res      <= not LOCK;


  DCM_BASE0 : DCM_BASE
    generic map (
      CLKDV_DIVIDE          => 16.0,  -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
      --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
      CLKFX_DIVIDE          => 8,       -- Can be any interger from 1 to 32
      CLKFX_MULTIPLY        => 2,       -- Can be any integer from 2 to 32
      CLKIN_DIVIDE_BY_2     => false,  -- TRUE/FALSE to enable CLKIN divide by two feature
      CLKIN_PERIOD          => 5.0,  -- Specify period of input clock in ns from 1.25 to 1000.00
      CLKOUT_PHASE_SHIFT    => "NONE",  -- Specify phase shift mode of NONE or FIXED
      CLK_FEEDBACK          => "1X",    -- Specify clock feedback of NONE or 1X
      DCM_AUTOCALIBRATION   => true,  -- DCM calibrartion circuitry TRUE/FALSE
      DCM_PERFORMANCE_MODE  => "MAX_SPEED",  -- Can be MAX_SPEED or MAX_RANGE
      DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS" ,  -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                        --   an integer from 0 to 15
      DFS_FREQUENCY_MODE    => "LOW",  -- LOW or HIGH frequency mode for frequency synthesis
      DLL_FREQUENCY_MODE    => "HIGH",  -- LOW, HIGH, or HIGH_SER frequency mode for DLL
      DUTY_CYCLE_CORRECTION => true,    -- Duty cycle correction, TRUE or FALSE
      FACTORY_JF            => X"F0F0",  -- FACTORY JF Values Suggested to be set to X"F0F0
      PHASE_SHIFT           => 0,  -- Amount of fixed phase shift from -255 to 1023
      STARTUP_WAIT          => false)  -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
    port map (
      CLK0     => CLK0_bufg_in ,  --CLK0_bufg_in,         -- 0 degree DCM CLK ouptput
      CLK180   => open,                 -- 180 degree DCM CLK output
      CLK270   => open,                 -- 270 degree DCM CLK output
      CLK2X    => open,                 -- 2X DCM CLK output
      CLK2X180 => open,                 -- 2X, 180 degree DCM CLK out
      CLK90    => clk90_bufg_in,        -- 90 degree DCM CLK output
      CLKDV    => clkdv_bufg_in,        -- Divided DCM CLK out (CLKDV_DIVIDE)
      CLKFX    => clk50_bufg_in,        -- DCM CLK synthesis out (M/D)
      CLKFX180 => open,                 -- 180 degree CLK synthesis out
      LOCKED   => dcm_lock,             -- DCM LOCK status output
      CLKFB    => clk0_bufg_out,  --CLK0_bufg_in,       -- DCM clock feedback
      CLKIN    => SYS_CLK_P ,       -- Clock input (from IBUFG, BUFG or DCM)
      RST      => dcm_lock_res          -- DCM asynchronous reset input
      );


  dcm_clk0 : BUFG
    port map (
      O => clk0_bufg_out,
      I => clk0_bufg_in
      );


  dcm_clk90 : BUFG
    port map (
      O => clk90_bufg_out,
      I => clk90_bufg_in
      );


  dcm_clkdv : BUFR
    port map (
      CE  => '1' ,
      CLR => '0' ,
      O   => clkdv_bufg_out,
      I   => clkdv_bufg_in
      );


  dcm_clkfx : BUFG
    port map (
      O => clk50_bufg_out,
      I => clk50_bufg_in
      );


  process(clk0_bufg_out)
  begin
    if clk0_bufg_out'event and clk0_bufg_out = '1' then

      if ((SYS_RESET = '1') or (dcm_lock = '0') or (sys_rst_ref_clk = '1')) then
        sys_rst_0 <= '1';
        sys_rst_1 <= '1';
        sys_rst_2 <= '1';
        sys_rst_3 <= '1';
        sys_rst   <= '1';
      else
        sys_rst_0 <= '0';
        sys_rst_1 <= sys_rst_0;
        sys_rst_2 <= sys_rst_1;
        sys_rst_3 <= sys_rst_2;
        sys_rst   <= sys_rst_3;

      end if;
    end if;
  end process;


  process(clk90_bufg_out)
  begin
    if clk90_bufg_out'event and clk90_bufg_out = '1' then

      if ((SYS_RESET = '1') or (dcm_lock = '0') or (sys_rst_ref_clk = '1')) then
        sys_rst90_0 <= '1';
        sys_rst90_1 <= '1';
        sys_rst90_2 <= '1';
        sys_rst90_3 <= '1';
        sys_rst90   <= '1';
      else
        sys_rst90_0 <= '0';
        sys_rst90_1 <= sys_rst90_0;
        sys_rst90_2 <= sys_rst90_1;
        sys_rst90_3 <= sys_rst90_2;
        sys_rst90   <= sys_rst90_3;
      end if;
    end if;
  end process;


  process(clk50_bufg_out)
  begin
    if clk50_bufg_out'event and clk50_bufg_out = '1' then

      if ((SYS_RESET = '1') or (dcm_lock = '0')) then
        sys_rst_ref_clk_0  <= '1';
        sys_rst_ref_clk_1r <= '1';
        sys_rst_ref_clk    <= '1';
      else
        sys_rst_ref_clk_0  <= '0';
        sys_rst_ref_clk_1r <= sys_rst_ref_clk_0;
        sys_rst_ref_clk    <= sys_rst_ref_clk_1r;
      end if;
    end if;
  end process;
  
end arc_infrastructure;

---

Author: M.Niegl

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