BCM-AAA: side_4rios.vhd Source File

00001 --**************************************************************
00002 --*                                                            *
00003 --*     The source code for the ATLAS BCM "AAA" FPGA is made   *
00004 --*     available via the GNU General Public License (GPL)     *
00005 --*     unless otherwise stated below.                         *
00006 --*                                                            *
00007 --*     In case of problems/questions/bug reports etc. please  *
00008 --*     contact michael.niegl@cern.ch                          *
00009 --*                                                            *
00010 --**************************************************************
00011 
00012 --**************************************************************
00013 --*                                                            *
00014 --*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/rio/side_4rios.vhd,v $
00015 --*  $Revision: 1.17.2.4 $                                         *
00016 --*  $Name: dev $                                              *
00017 --*  $Author: mniegl $                                         *
00018 --*  $Date: 2008/11/03 17:57:48 $                              *
00019 
00020 
00021 --*                                                            *
00022 --**************************************************************
00023 
00024 library ieee;
00025 
00026 use ieee.std_logic_1164.all;
00027 
00028 use ieee.std_logic_arith.all;
00029 
00030 use ieee.std_logic_unsigned.all;
00031 library work;
00032 use work.daq_header.all;
00033 
00034 library unisim;
00035 
00036 use unisim.vcomponents.all;
00037 
00038 
00039 entity side_4rios is
00040   generic
00041     (
00042       PATTERN : std_logic_vector(31 downto 0) := "11110000111100001111000011110000"
00043       );
00044   port
00045     (
00046       BCLK                : in  std_logic;
00047       BCLK2X              : in  std_logic;
00048       BCLK4X              : in  std_logic;
00049       RIOCLK_1            : in  std_logic;
00050       RIOCLK_2            : in  std_logic;
00051       EN                  : in  std_logic;
00052       SET_SHIFT_1         : in  std_logic_vector(7 downto 0);
00053       SET_SHIFT_2         : in  std_logic_vector(7 downto 0);
00054       CAL                 : in  std_logic;
00055       CHECK_IRENA         : out std_logic;
00056       CHECK_EWA           : out std_logic;
00057       CHECK_ANDREJ        : out std_logic;
00058       CHECK_HEINZ         : out std_logic;
00059       CAL_IRENA           : in  std_logic;
00060       CAL_EWA             : in  std_logic;
00061       CAL_ANDREJ          : in  std_logic;
00062       CAL_HEINZ           : in  std_logic;
00063       RES                 : in  std_logic;
00064       SEP_RES             : in  std_logic_vector(3 downto 0);
00065       TX_SYSTEM_RESET_IN  : in  std_logic;
00066       RX_SYSTEM_RESET_IN  : in  std_logic;
00067       COARSE_TIME_IRENA   : in  std_logic_vector(7 downto 0);
00068       COARSE_TIME_EWA     : in  std_logic_vector(7 downto 0);
00069       COARSE_TIME_ANDREJ  : in  std_logic_vector(7 downto 0);
00070       COARSE_TIME_HEINZ   : in  std_logic_vector(7 downto 0);
00071       ADJUST_TIME_IRENA   : in  integer range 0 to 32;
00072       ADJUST_TIME_EWA     : in  integer range 0 to 32;
00073       ADJUST_TIME_ANDREJ  : in  integer range 0 to 32;
00074       ADJUST_TIME_HEINZ   : in  integer range 0 to 32;
00075       ADJUST_TIME_IRENA2  : in  integer range 0 to 32;
00076       ADJUST_TIME_EWA2    : in  integer range 0 to 32;
00077       ADJUST_TIME_ANDREJ2 : in  integer range 0 to 32;
00078       ADJUST_TIME_HEINZ2  : in  integer range 0 to 32;
00079       RXLOCK_OUT_IRENA    : out std_logic;
00080       TXLOCK_OUT_IRENA    : out std_logic;
00081       RXLOCK_OUT_EWA      : out std_logic;
00082       TXLOCK_OUT_EWA      : out std_logic;
00083       RXLOCK_OUT_ANDREJ   : out std_logic;
00084       TXLOCK_OUT_ANDREJ   : out std_logic;
00085       RXLOCK_OUT_HEINZ    : out std_logic;
00086       TXLOCK_OUT_HEINZ    : out std_logic;
00087       RX1N_IN_IE          : in  std_logic_vector(1 downto 0);
00088       RX1P_IN_IE          : in  std_logic_vector(1 downto 0);
00089       TX1N_OUT_IE         : out std_logic_vector(1 downto 0);
00090       TX1P_OUT_IE         : out std_logic_vector(1 downto 0);
00091       RX1N_IN_AH          : in  std_logic_vector(1 downto 0);
00092       RX1P_IN_AH          : in  std_logic_vector(1 downto 0);
00093       TX1N_OUT_AH         : out std_logic_vector(1 downto 0);
00094       TX1P_OUT_AH         : out std_logic_vector(1 downto 0);
00095       RX_READY_FLAG_IE    : out std_logic;
00096       TX_READY_FLAG_IE    : out std_logic;
00097       RX_READY_FLAG_AH    : out std_logic;
00098       TX_READY_FLAG_AH    : out std_logic;
00099       SUM_RIS_IRENA       : out std_logic_vector (7 downto 0);
00100       SUM_FAL_IRENA       : out std_logic_vector (7 downto 0);
00101       T1_IRENA            : out std_logic_vector (7 downto 0);
00102       T2_IRENA            : out std_logic_vector (7 downto 0);
00103       T3_IRENA            : out std_logic_vector (7 downto 0);
00104       W1_IRENA            : out std_logic_vector (7 downto 0);
00105       W2_IRENA            : out std_logic_vector (7 downto 0);
00106       W3_IRENA            : out std_logic_vector (7 downto 0);
00107       STATUS_T1_IRENA     : out std_logic;
00108       STATUS_T2_IRENA     : out std_logic;
00109       STATUS_T3_IRENA     : out std_logic;
00110       STATUS_W1_IRENA     : out std_logic;
00111       STATUS_W2_IRENA     : out std_logic;
00112       STATUS_W3_IRENA     : out std_logic;
00113       OVERFLOW_IRENA      : out std_logic;
00114       SUM_RIS_EWA         : out std_logic_vector (7 downto 0);
00115       SUM_FAL_EWA         : out std_logic_vector (7 downto 0);
00116       T1_EWA              : out std_logic_vector (7 downto 0);
00117       T2_EWA              : out std_logic_vector (7 downto 0);
00118       T3_EWA              : out std_logic_vector (7 downto 0);
00119       W1_EWA              : out std_logic_vector (7 downto 0);
00120       W2_EWA              : out std_logic_vector (7 downto 0);
00121       W3_EWA              : out std_logic_vector (7 downto 0);
00122       STATUS_T1_EWA       : out std_logic;
00123       STATUS_T2_EWA       : out std_logic;
00124       STATUS_T3_EWA       : out std_logic;
00125       STATUS_W1_EWA       : out std_logic;
00126       STATUS_W2_EWA       : out std_logic;
00127       STATUS_W3_EWA       : out std_logic;
00128       OVERFLOW_EWA        : out std_logic;
00129       SUM_RIS_ANDREJ      : out std_logic_vector (7 downto 0);
00130       SUM_FAL_ANDREJ      : out std_logic_vector (7 downto 0);
00131       T1_ANDREJ           : out std_logic_vector (7 downto 0);
00132       T2_ANDREJ           : out std_logic_vector (7 downto 0);
00133       T3_ANDREJ           : out std_logic_vector (7 downto 0);
00134       W1_ANDREJ           : out std_logic_vector (7 downto 0);
00135       W2_ANDREJ           : out std_logic_vector (7 downto 0);
00136       W3_ANDREJ           : out std_logic_vector (7 downto 0);
00137       STATUS_T1_ANDREJ    : out std_logic;
00138       STATUS_T2_ANDREJ    : out std_logic;
00139       STATUS_T3_ANDREJ    : out std_logic;
00140       STATUS_W1_ANDREJ    : out std_logic;
00141       STATUS_W2_ANDREJ    : out std_logic;
00142       STATUS_W3_ANDREJ    : out std_logic;
00143       OVERFLOW_ANDREJ     : out std_logic;
00144       SUM_RIS_HEINZ       : out std_logic_vector (7 downto 0);
00145       SUM_FAL_HEINZ       : out std_logic_vector (7 downto 0);
00146       T1_HEINZ            : out std_logic_vector (7 downto 0);
00147       T2_HEINZ            : out std_logic_vector (7 downto 0);
00148       T3_HEINZ            : out std_logic_vector (7 downto 0);
00149       W1_HEINZ            : out std_logic_vector (7 downto 0);
00150       W2_HEINZ            : out std_logic_vector (7 downto 0);
00151       W3_HEINZ            : out std_logic_vector (7 downto 0);
00152       STATUS_T1_HEINZ     : out std_logic;
00153       STATUS_T2_HEINZ     : out std_logic;
00154       STATUS_T3_HEINZ     : out std_logic;
00155       STATUS_W1_HEINZ     : out std_logic;
00156       STATUS_W2_HEINZ     : out std_logic;
00157       STATUS_W3_HEINZ     : out std_logic;
00158       OVERFLOW_HEINZ      : out std_logic;
00159       MASK_IRENA          : out std_logic;
00160       MASK_EWA            : out std_logic;
00161       MASK_ANDREJ         : out std_logic;
00162       MASK_HEINZ          : out std_logic;
00163       CAL_DONE            : out std_logic;
00164       RAW_DATA_IRENA      : out std_logic_vector(31 downto 0);
00165       RAW_DATA_EWA        : out std_logic_vector(31 downto 0);
00166       RAW_DATA_ANDREJ     : out std_logic_vector(31 downto 0);
00167       RAW_DATA_HEINZ      : out std_logic_vector(31 downto 0)
00168       );         
00169 end side_4rios;
00170 
00171 
00172 architecture side_4rios_arc of side_4rios is
00173 
00174 --*************************** Signal Declarations *****************************
00175   signal done1 : std_logic := '0';
00176   signal done2 : std_logic := '0';
00177   signal res1  : std_logic := '0';
00178   signal res2  : std_logic := '0';
00179 
00180 --************************** Component Declarations ***************************
00181 
00182   component daqrio_top
00183     generic
00184       (
00185         PATTERN : std_logic_vector(31 downto 0) := x"f0f0f0f0"
00186         );
00187     port(
00188       SET_SHIFT          : in  std_logic_vector(7 downto 0);
00189       CALIB              : in  std_logic;
00190       CAL1               : in  std_logic;
00191       CAL2               : in  std_logic;
00192       RES                : in  std_logic;
00193       REF                : in  std_logic;
00194       PAR                : in  std_logic;
00195       BC                 : in  std_logic;
00196       EN                 : in  std_logic;
00197       TX_SYSTEM_RESET_IN : in  std_logic;
00198       RX_SYSTEM_RESET_IN : in  std_logic;
00199       RX1N_IN            : in  std_logic_vector(1 downto 0);
00200       RX1P_IN            : in  std_logic_vector(1 downto 0);
00201       CHECK_1            : out std_logic;
00202       CHECK_2            : out std_logic;
00203       MGT0_RXLOCK_OUT    : out std_logic;
00204       MGT0_TXLOCK_OUT    : out std_logic;
00205       MGT1_RXLOCK_OUT    : out std_logic;
00206       MGT1_TXLOCK_OUT    : out std_logic;
00207       TX1N_OUT           : out std_logic_vector(1 downto 0);
00208       TX1P_OUT           : out std_logic_vector(1 downto 0);
00209       RX_READY_FLAG      : out std_logic;
00210       TX_READY_FLAG      : out std_logic;
00211       PULSE_OUT_P        : out std_logic;
00212       SUM_RIS_1          : out std_logic_vector(7 downto 0);
00213       SUM_FAL_1          : out std_logic_vector(7 downto 0);
00214       T1_1               : out std_logic_vector(7 downto 0);
00215       T2_1               : out std_logic_vector(7 downto 0);
00216       T3_1               : out std_logic_vector(7 downto 0);
00217       W1_1               : out std_logic_vector(7 downto 0);
00218       W2_1               : out std_logic_vector(7 downto 0);
00219       W3_1               : out std_logic_vector(7 downto 0);
00220       STATUS_T1_1        : out std_logic;
00221       STATUS_T2_1        : out std_logic;
00222       STATUS_T3_1        : out std_logic;
00223       STATUS_W1_1        : out std_logic;
00224       STATUS_W2_1        : out std_logic;
00225       STATUS_W3_1        : out std_logic;
00226       OVERFLOW_1         : out std_logic;
00227       SUM_RIS_2          : out std_logic_vector(7 downto 0);
00228       SUM_FAL_2          : out std_logic_vector(7 downto 0);
00229       T1_2               : out std_logic_vector(7 downto 0);
00230       T2_2               : out std_logic_vector(7 downto 0);
00231       T3_2               : out std_logic_vector(7 downto 0);
00232       W1_2               : out std_logic_vector(7 downto 0);
00233       W2_2               : out std_logic_vector(7 downto 0);
00234       W3_2               : out std_logic_vector(7 downto 0);
00235       STATUS_T1_2        : out std_logic;
00236       STATUS_T2_2        : out std_logic;
00237       STATUS_T3_2        : out std_logic;
00238       STATUS_W1_2        : out std_logic;
00239       STATUS_W2_2        : out std_logic;
00240       STATUS_W3_2        : out std_logic;
00241       OVERFLOW_2         : out std_logic;
00242       MASK_1             : out std_logic;
00243       MASK_2             : out std_logic;
00244       CALIB_DONE         : out std_logic;
00245       RAW_DATA1          : out std_logic_vector(31 downto 0);
00246       RAW_DATA2          : out std_logic_vector(31 downto 0);
00247       COARSE_TIME_1      : in  std_logic_vector(7 downto 0);
00248       COARSE_TIME_2      : in  std_logic_vector(7 downto 0);
00249       ADJUST_TIME_1      : in  integer range 0 to 32;
00250       ADJUST_TIME_2      : in  integer range 0 to 32;
00251       ADJUST_TIME_12     : in  integer range 0 to 32;
00252       ADJUST_TIME_22     : in  integer range 0 to 32
00253       );
00254   end component;
00255 
00256 
00257   component NULL_PAIR
00258     port (
00259       GREFCLK_IN : in  std_logic;
00260       RX1N_IN    : in  std_logic_vector(1 downto 0);
00261       RX1P_IN    : in  std_logic_vector(1 downto 0);
00262       TX1N_OUT   : out std_logic_vector(1 downto 0);
00263       TX1P_OUT   : out std_logic_vector(1 downto 0));   
00264   end component;
00265 
00266   attribute box_type              : string;
00267   attribute box_type of NULL_PAIR : component is "user_black_box";
00268 
00269 --*************************************************************************
00270 --                                 main code
00271 --*************************************************************************
00272 
00273 begin
00274 
00275   CAL_DONE <= done1 and done2;
00276   res1     <= SEP_RES(0) or SEP_RES(1) or RES;
00277   res2     <= SEP_RES(2) or SEP_RES(3) or RES;
00278 
00279 
00280   Irena_Ewa : daqrio_top
00281     generic map
00282     (
00283       PATTERN => PATTERN
00284       )
00285     port map
00286     (
00287       SET_SHIFT          => SET_SHIFT_1,
00288       CHECK_1            => CHECK_IRENA,
00289       CHECK_2            => CHECK_EWA,
00290       CALIB              => CAL,
00291       CAL1               => CAL_IRENA,
00292       CAL2               => CAL_EWA,
00293       RES                => res1,
00294       REF                => RIOCLK_1,
00295       BC                 => BCLK,
00296       PAR                => BCLK2X,
00297       EN                 => EN,
00298       TX_SYSTEM_RESET_IN => '0',
00299       RX_SYSTEM_RESET_IN => '0',
00300       MGT0_RXLOCK_OUT    => RXLOCK_OUT_IRENA,
00301       MGT0_TXLOCK_OUT    => TXLOCK_OUT_IRENA,
00302       MGT1_RXLOCK_OUT    => RXLOCK_OUT_EWA,
00303       MGT1_TXLOCK_OUT    => TXLOCK_OUT_EWA,
00304       RX1N_IN             => RX1N_IN_IE,
00305       RX1P_IN             => RX1P_IN_IE,
00306       TX1N_OUT           => TX1N_OUT_IE,
00307       TX1P_OUT           => TX1P_OUT_IE,
00308       RX_READY_FLAG      => RX_READY_FLAG_IE,
00309       TX_READY_FLAG      => TX_READY_FLAG_IE,
00310       PULSE_OUT_P        => open,
00311       SUM_RIS_1          => SUM_RIS_IRENA,
00312       SUM_FAL_1          => SUM_FAL_IRENA,
00313       T1_1               => T1_IRENA,
00314       T2_1               => T2_IRENA,
00315       T3_1               => T3_IRENA,
00316       W1_1               => W1_IRENA,
00317       W2_1               => W2_IRENA,
00318       W3_1               => W3_IRENA,
00319       STATUS_T1_1        => STATUS_T1_IRENA ,
00320       STATUS_T2_1        => STATUS_T2_IRENA ,
00321       STATUS_T3_1        => STATUS_T3_IRENA ,
00322       STATUS_W1_1        => STATUS_W1_IRENA ,
00323       STATUS_W2_1        => STATUS_W2_IRENA ,
00324       STATUS_W3_1        => STATUS_W3_IRENA ,
00325       OVERFLOW_1         => OVERFLOW_IRENA,
00326       SUM_RIS_2          => SUM_RIS_EWA,
00327       SUM_FAL_2          => SUM_FAL_EWA,
00328       T1_2               => T1_EWA,
00329       T2_2               => T2_EWA,
00330       T3_2               => T3_EWA,
00331       W1_2               => W1_EWA,
00332       W2_2               => W2_EWA,
00333       W3_2               => W3_EWA,
00334       STATUS_T1_2        => STATUS_T1_EWA,
00335       STATUS_T2_2        => STATUS_T2_EWA,
00336       STATUS_T3_2        => STATUS_T3_EWA,
00337       STATUS_W1_2        => STATUS_W1_EWA,
00338       STATUS_W2_2        => STATUS_W2_EWA,
00339       STATUS_W3_2        => STATUS_W3_EWA,
00340       OVERFLOW_2         => OVERFLOW_EWA,
00341       MASK_1             => MASK_IRENA,
00342       MASK_2             => MASK_EWA,
00343       CALIB_DONE         => done1,
00344       RAW_DATA1          => RAW_DATA_IRENA,
00345       RAW_DATA2          => RAW_DATA_EWA,
00346       COARSE_TIME_1      => COARSE_TIME_IRENA ,
00347       COARSE_TIME_2      => COARSE_TIME_EWA,
00348       ADJUST_TIME_1      => ADJUST_TIME_IRENA ,
00349       ADJUST_TIME_2      => ADJUST_TIME_EWA,
00350       ADJUST_TIME_12     => ADJUST_TIME_IRENA2 ,
00351       ADJUST_TIME_22     => ADJUST_TIME_EWA2
00352       );
00353 
00354 
00355   Andrej_Heinz : daqrio_top
00356     generic map
00357     (
00358       PATTERN => PATTERN
00359       )
00360     port map
00361     (
00362       SET_SHIFT          => SET_SHIFT_1,
00363       CHECK_1            => CHECK_ANDREJ,
00364       CHECK_2            => CHECK_HEINZ,
00365       CALIB              => CAL,
00366       CAL1               => CAL_ANDREJ,
00367       CAL2               => CAL_HEINZ,
00368       RES                => res2,
00369       REF                => RIOCLK_1,
00370       PAR                => BCLK2X,
00371       BC                 => BCLK,
00372       EN                 => EN,
00373       TX_SYSTEM_RESET_IN => '0',
00374       RX_SYSTEM_RESET_IN => '0',
00375       MGT0_RXLOCK_OUT    => RXLOCK_OUT_ANDREJ,
00376       MGT0_TXLOCK_OUT    => TXLOCK_OUT_ANDREJ,
00377       MGT1_RXLOCK_OUT    => RXLOCK_OUT_HEINZ,
00378       MGT1_TXLOCK_OUT    => TXLOCK_OUT_HEINZ,
00379       RX1N_IN             => RX1N_IN_AH,
00380       RX1P_IN            => RX1P_IN_AH,
00381       TX1N_OUT           => TX1N_OUT_AH,
00382       TX1P_OUT           => TX1P_OUT_AH,
00383       RX_READY_FLAG      => RX_READY_FLAG_AH,
00384       TX_READY_FLAG      => TX_READY_FLAG_AH,
00385       PULSE_OUT_P        => open,
00386       SUM_RIS_1          => SUM_RIS_ANDREJ,
00387       SUM_FAL_1          => SUM_FAL_ANDREJ,
00388       T1_1               => T1_ANDREJ,
00389       T2_1               => T2_ANDREJ ,
00390       T3_1               => T3_ANDREJ,
00391       W1_1               => W1_ANDREJ ,
00392       W2_1                => W2_ANDREJ,
00393       W3_1                => W3_ANDREJ,
00394       STATUS_T1_1        => STATUS_T1_ANDREJ ,
00395       STATUS_T2_1        => STATUS_T2_ANDREJ ,
00396       STATUS_T3_1        => STATUS_T3_ANDREJ ,
00397       STATUS_W1_1        => STATUS_W1_ANDREJ ,
00398       STATUS_W2_1        => STATUS_W2_ANDREJ ,
00399       STATUS_W3_1        => STATUS_W3_ANDREJ ,
00400       OVERFLOW_1         => OVERFLOW_ANDREJ ,
00401       SUM_RIS_2          => SUM_RIS_HEINZ,
00402       SUM_FAL_2          => SUM_FAL_HEINZ,
00403       T1_2                => T1_HEINZ,
00404       T2_2               => T2_HEINZ,
00405       T3_2               => T3_HEINZ,
00406       W1_2               => W1_HEINZ,
00407       W2_2               => W2_HEINZ,
00408       W3_2               => W3_HEINZ,
00409       STATUS_T1_2        => STATUS_T1_HEINZ ,
00410       STATUS_T2_2        => STATUS_T2_HEINZ ,
00411       STATUS_T3_2        => STATUS_T3_HEINZ ,
00412       STATUS_W1_2        => STATUS_W1_HEINZ ,
00413       STATUS_W2_2        => STATUS_W2_HEINZ ,
00414       STATUS_W3_2        => STATUS_W3_HEINZ ,
00415       OVERFLOW_2         => OVERFLOW_HEINZ,
00416       MASK_1              => MASK_ANDREJ,
00417       MASK_2              => MASK_HEINZ,
00418       CALIB_DONE         => done2,
00419       RAW_DATA1          => RAW_DATA_ANDREJ ,
00420       RAW_DATA2          => RAW_DATA_HEINZ,
00421       COARSE_TIME_1      => COARSE_TIME_ANDREJ ,
00422       COARSE_TIME_2      => COARSE_TIME_HEINZ ,
00423       ADJUST_TIME_1      => ADJUST_TIME_ANDREJ ,
00424       ADJUST_TIME_2      => ADJUST_TIME_HEINZ ,
00425       ADJUST_TIME_12     => ADJUST_TIME_ANDREJ2 ,
00426       ADJUST_TIME_22     => ADJUST_TIME_HEINZ2 
00427       );
00428 
00429 end side_4rios_arc;
00430