edge_det.vhd

Go to the documentation of this file.

--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/rio/edge_det.vhd,v $                                                  *
--*  $Revision: 1.7.2.6 $                                                *
--*  $Name: dev $                                                    *
--*  $Author: mniegl $                                                  *
--*  $Date: 2008/11/03 17:57:47 $                                                    *


--*                                                            *
--**************************************************************


library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;
library work;
use work.daq_header.all;









entity edge_det is
  port (
    DATA_IN   : in  std_logic_vector (31 downto 0);
    CLK       : in  std_logic;
    SUM_RIS   : out std_logic_vector (5 downto 0);
    SUM_FAL   : out std_logic_vector (5 downto 0);
    EDGE_RIS1 : out std_logic_vector (4 downto 0);
    EDGE_RIS2 : out std_logic_vector (4 downto 0);
    EDGE_RIS3 : out std_logic_vector (4 downto 0);
    EDGE_FAL1 : out std_logic_vector (4 downto 0);
    EDGE_FAL2 : out std_logic_vector (4 downto 0);
    EDGE_FAL3 : out std_logic_vector (4 downto 0);
    STATUS_P1 : out std_logic;
    STATUS_P2 : out std_logic;
    STATUS_P3 : out std_logic;
    STATUS_N1 : out std_logic;
    STATUS_N2 : out std_logic;
    STATUS_N3 : out std_logic
    );
end edge_det;

------------------------------------------------------------------------------
------------------------------------------------------------------------------








architecture new2 of edge_det is

----------------------------- signals --------------------------------------
  signal index_p1_latch     : sixteen;
  signal index_n1_latch     : sixteen;
  signal index_p_low        : eight;
  signal index_n_low        : eight;
  signal index_p1_latch2    : four;
  signal index_n1_latch2    : four;
  signal index_p1_latch3    : four;
  signal index_n1_latch3    : four;
  signal sum1_n             : twofour;
  signal sum2_n             : fivetwo;
  signal sum1_p             : twofour;
  signal sum2_p             : fivetwo;
  signal data_old           : std_logic_vector (2 downto 0)  := "000";
  signal data_i             : std_logic_vector (34 downto 0) := (others => '0');
  signal data_ii            : std_logic_vector (34 downto 0) := (others => '0');
  signal data_i_filt        : std_logic_vector (34 downto 0) := (others => '0');
  signal data_ii_filt       : std_logic_vector (34 downto 0) := (others => '0');
--  signal data_i2            : std_logic_vector (34 downto 0) := (others => '0');
--  signal data_ii2           : std_logic_vector (34 downto 0) := (others => '0');
  signal fdata_i            : std_logic_vector (34 downto 0) := (others => '0');
  signal fdata_ii           : std_logic_vector (34 downto 0) := (others => '0');
--  signal fdata_i2           : std_logic_vector (34 downto 0) := (others => '0');
--  signal fdata_ii2          : std_logic_vector (34 downto 0) := (others => '0');
  signal edge_det_p         : std_logic_vector (32 downto 1) := (others => '0');
  signal edge_det_p2        : std_logic_vector (32 downto 1) := (others => '0');
  signal edge_det_n         : std_logic_vector (32 downto 1) := (others => '0');
--  signal edge_det_nh        : std_logic_vector (32 downto 1) := (others => '0');
--  signal edge_det_ph        : std_logic_vector (32 downto 1) := (others => '0');
--  signal edge_det_nhh       : std_logic_vector (32 downto 1) := (others => '0');
--  signal edge_det_phh       : std_logic_vector (32 downto 1) := (others => '0');


  signal status1_p1         : std_logic_vector (8 downto 1)  := "00000000";
  signal status11_p1        : std_logic_vector (4 downto 1)  := "0000";
  signal status2_p1         : std_logic_vector (2 downto 1)  := "00";
  signal status1_p2         : std_logic_vector (2 downto 1)  := "00";
  signal status12_p2        : std_logic                      := '0';
  signal status1_p3         : std_logic_vector (2 downto 1)  := "00";
  signal status12_p3        : std_logic                      := '0';
  signal status1_n1         : std_logic_vector (8 downto 1)  := "00000000";
  signal status11_n1        : std_logic_vector (4 downto 1)  := "0000";
  signal status2_n1         : std_logic_vector (2 downto 1)  := "00";
  signal status_i_p1        : std_logic                      := '0';
  signal status_i_n1        : std_logic                      := '0';
  signal status1_n2         : std_logic_vector (2 downto 1)  := "00";
  signal status12_n2        : std_logic                      := '0';
  signal status1_n3         : std_logic_vector (2 downto 1)  := "00";
  signal status12_n3        : std_logic                      := '0';
  signal index_p1_latch22   : std_logic_vector (1 downto 0)  := "00";
  signal index_n1_latch22   : std_logic_vector (1 downto 0)  := "00";
  signal index_p1_latch33   : std_logic_vector (1 downto 0)  := "00";
  signal index_n1_latch33   : std_logic_vector (1 downto 0)  := "00";
  signal index_p1_latch4    : std_logic                      := '0';
  signal index_n1_latch4    : std_logic                      := '0';
  signal index_p2_latch     : std_logic_vector (1 downto 0)  := "00";
  signal index_p2_latch3    : std_logic_vector (2 downto 0)  := "000";
  signal index_p2_latch33   : std_logic_vector (1 downto 0)  := "00";
  signal index_p2_latch33_1 : std_logic_vector (2 downto 0)  := "000";
  signal index_p2_out_1     : std_logic_vector (1 downto 0)  := "00";
  signal index_p2_out       : std_logic_vector (1 downto 0)  := "00";
  signal index_n2_latch     : std_logic_vector (1 downto 0)  := "00";
  signal index_n2_latch3    : std_logic_vector (2 downto 0)  := "000";
  signal index_n2_latch33   : std_logic_vector (1 downto 0)  := "00";
  signal index_n2_latch33_1 : std_logic_vector (2 downto 0)  := "000";
  signal index_n2_out_1     : std_logic_vector (1 downto 0)  := "00";
  signal index_n2_out       : std_logic_vector (1 downto 0)  := "00";
  signal index_p3_latch     : std_logic_vector (1 downto 0)  := "00";
  signal index_p3_latch3    : std_logic_vector (2 downto 0)  := "000";
  signal index_p3_latch33   : std_logic_vector (1 downto 0)  := "00";
  signal index_p3_latch33_1 : std_logic_vector (2 downto 0)  := "000";
  signal index_p3_out       : std_logic_vector (1 downto 0)  := "00";
  signal index_p3_out_1     : std_logic_vector (1 downto 0)  := "00";
  signal index_n3_latch     : std_logic_vector (1 downto 0)  := "00";
  signal index_n3_latch3    : std_logic_vector (2 downto 0)  := "000";
  signal index_n3_latch33   : std_logic_vector (1 downto 0)  := "00";
  signal index_n3_latch33_1 : std_logic_vector (2 downto 0)  := "000";
  signal index_n3_out       : std_logic_vector (1 downto 0)  := "00";
  signal index_n3_out_1     : std_logic_vector (1 downto 0)  := "00";
  signal sum_p              : std_logic_vector (5 downto 0)  := "000000";
  signal sum_n              : std_logic_vector (5 downto 0)  := "000000";
  signal SUM_RIS_i          : std_logic_vector (5 downto 0)  := "000000";
  signal SUM_FAL_i          : std_logic_vector (5 downto 0)  := "000000";
  signal STATUS_P1_i        : std_logic                      := '0';
  signal STATUS_P2_i        : std_logic                      := '0';
  signal STATUS_P3_i        : std_logic                      := '0';
  signal STATUS_N1_i        : std_logic                      := '0';
  signal STATUS_N2_i        : std_logic                      := '0';
  signal STATUS_N3_i        : std_logic                      := '0';
  signal EDGE_RIS1_i        : std_logic_vector (4 downto 0)  := "00000";
  signal EDGE_RIS2_i        : std_logic_vector (4 downto 0)  := "00000";
  signal EDGE_RIS3_i        : std_logic_vector (4 downto 0)  := "00000";
  signal EDGE_FAL1_i        : std_logic_vector (4 downto 0)  := "00000";
  signal EDGE_FAL2_i        : std_logic_vector (4 downto 0)  := "00000";
  signal EDGE_FAL3_i        : std_logic_vector (4 downto 0)  := "00000";

begin


  process(CLK)
------------------------------- variables -------------------------------------
    variable index_p2_latch333            : std_logic_vector (1 downto 0)  := "00";
    variable index_n2_latch333            : std_logic_vector (1 downto 0)  := "00";
    variable index_p3_latch333            : std_logic_vector (1 downto 0)  := "00";
    variable index_n3_latch333            : std_logic_vector (1 downto 0)  := "00";
    variable fill1, fill2                 : std_logic_vector (34 downto 0) := (others => '0');
    variable edge_det_nh                  : std_logic_vector (32 downto 1) := (others => '0');
    variable edge_det_ph                  : std_logic_vector (32 downto 1) := (others => '0');
    variable edge_det_nhh                 : std_logic_vector (32 downto 1) := (others => '0');
    variable edge_det_phh                 : std_logic_vector (32 downto 1) := (others => '0');
    variable spike_p                      : std_logic_vector (32 downto 1) := (others => '1');
    variable spike_n                      : std_logic_vector (32 downto 1) := (others => '1');
    variable a, b, c, e, f, x, k, l, m, n : std_logic                      := '0';
    
  begin

    if CLK'event and CLK = '1' then

------------------------------- default values -------------------------------------    
      status1_p1                  <= (others => '1');
      status1_n1                  <= (others => '1');
      status2_p1                  <= (others => '1');
      status2_n1                  <= (others => '1');
      spike_n                     := (others => '1');
      spike_p                     := (others => '1');
      status_i_p1                 <= '1';
      status_i_n1                 <= '1';
      status1_p2                  <= "11";
      status12_p2                 <= '1';
      index_p2_latch3(2 downto 0) <= "111";
      status1_n2                  <= "11";
      status12_n2                 <= '1';
      index_n2_latch3(2 downto 0) <= "111";
      index_n2_latch33            <= "11";
      index_n2_latch333           := "11";
      status1_p3                  <= "11";
      status12_p3                 <= '1';
      index_p3_latch3(2 downto 0) <= "111";
      status1_n3                  <= "11";
      status12_n3                 <= '1';
      index_n3_latch3(2 downto 0) <= "111";
      index_n3_latch33            <= "11";
      index_n3_latch333           := "11";

      data_old <= DATA_IN(2 downto 0);
      data_i   <= data_old & DATA_IN;
      data_ii  <= data_i(31 downto 0) & DATA_IN(31 downto 29);

------------------------------ filtering --------------------------------------      
      for i in (DATA_IN'length+2) downto 3 loop  --edge det via pattern matching, ris and fal
        edge_det_ph(i-2)  := ris_hole_pattern(data_i(i downto i-3));
        edge_det_nh(i-2)  := fal_hole_pattern(data_i(i downto i-3));
        edge_det_phh(i-2) := ris_hole_pattern(data_ii(i downto i-3));
        edge_det_nhh(i-2) := fal_hole_pattern(data_ii(i downto i-3));
      end loop;

      fill1 := ("00" & edge_det_ph & '0') or ('0' & edge_det_nh & "00");
      fill2 := ("00" & edge_det_phh & '0') or ('0' & edge_det_nhh & "00");

--      data_i2  <= data_i;
--      data_ii2 <= data_ii;

      fdata_i  <= data_i or fill1;
      fdata_ii <= data_ii or fill2;

----------------------------- spike suppression ----------------------------------- 
      for i in (DATA_IN'length+2) downto 3 loop
        spike_p(i-2) := spike_suppress(fdata_i(i downto i-2));
        spike_n(i-2) := spike_suppress(fdata_ii(i downto i-2));
      end loop;

--      fdata_i2  <= fdata_i;
--      fdata_ii2 <= fdata_ii;

      data_i_filt  <= fdata_i and ('1' & spike_p & "11");
      data_ii_filt <= fdata_ii and ('1' & spike_n & "11");

------------------------------- edge det -------------------------------------                  
      for i in (DATA_IN'length+2) downto 3 loop  --edge det via pattern matching, ris and fal
        edge_det_p2(i-2) <= ris_pattern(data_i_filt(i downto i-3));
        edge_det_n(i-2)  <= fal_pattern(data_ii_filt(i downto i-3));
      end loop;

      edge_det_p <= edge_det_p2;

------------------------------- pos 1 r & f -------------------------------------                               
      for m in 1 to 8 loop              -- 8 status bits, LSBs of pos1
        if edge_det_p((m*4)) = '1' then
          index_p1_latch(m) <= "11";
        elsif edge_det_p((m*4)-1) = '1' then
          index_p1_latch(m) <= "10";
        elsif edge_det_p((m*4)-2) = '1' then
          index_p1_latch(m) <= "01";
        elsif edge_det_p((m*4)-3) = '1' then
          index_p1_latch(m) <= "00";
        else
          status1_p1(m) <= '0';
        end if;
        
        sum1_p(m) <= conv_std_logic_vector((conv_integer(edge_det_p(m*4)) +
                                            conv_integer(edge_det_p((m*4)-1)) +
                                            conv_integer(edge_det_p((m*4)-2)) +
                                            conv_integer(edge_det_p((m*4)-3))),3);

        if edge_det_n((m*4)) = '1' then
          index_n1_latch(m) <= "11";
        elsif edge_det_n((m*4)-1) = '1' then
          index_n1_latch(m) <= "10";
        elsif edge_det_n((m*4)-2) = '1' then
          index_n1_latch(m) <= "01";
        elsif edge_det_n((m*4)-3) = '1' then
          index_n1_latch(m) <= "00";
        else
          status1_n1(m) <= '0';
        end if;
        
        sum1_n(m) <= conv_std_logic_vector((conv_integer(edge_det_n(m*4)) +
                                            conv_integer(edge_det_n((m*4)-1)) +
                                            conv_integer(edge_det_n((m*4)-2)) +
                                            conv_integer(edge_det_n((m*4)-3))),3);

      end loop;

------------------------------- search top 4 bits for 2nd edge -------------------------------------                    
      a := dec13 (status1_p1(8 downto 6));
      c := dec13 (status1_n1(8 downto 6));

      if (status1_p1(7) and status1_p1(8)) = '1' then  --search top 4 bit for 2nd edge
        index_p2_latch3(1 downto 0) <= "10";
        index_p2_latch              <= index_p1_latch(7);
      elsif (status1_p1(6) and
             (status1_p1(7) xor status1_p1(8))) = '1' then
        index_p2_latch3(1 downto 0) <= "01";
        index_p2_latch              <= index_p1_latch(6);
      elsif (status1_p1(5) and a) = '1' then
        index_p2_latch3(1 downto 0) <= "00";
        index_p2_latch              <= index_p1_latch(5);
      else
        status12_p2                 <= '0';
        index_p2_latch3(2 downto 0) <= "000";
        index_p2_latch              <= "00";
      end if;

      if (status1_n1(7) and status1_n1(8)) = '1' then
        index_n2_latch3(1 downto 0) <= "10";
        index_n2_latch              <= index_n1_latch(7);
      elsif (status1_n1(6) and (status1_n1(7) xor status1_n1(8))) = '1' then
        index_n2_latch3(1 downto 0) <= "01";
        index_n2_latch              <= index_n1_latch(6);
      elsif (status1_n1(5) and c) = '1' then
        index_n2_latch3(1 downto 0) <= "00";
        index_n2_latch              <= index_n1_latch(5);
      else
        status12_n2                 <= '0';
        index_n2_latch3(2 downto 0) <= "000";
        index_n2_latch              <= "00";
      end if;

--------------------------------- search top 4 bits for 3rd edge -------------------------------------                  
      k := dec23 (status1_p1(8 downto 6));
      l := dec23 (status1_n1(8 downto 6));

      if (status1_p1(8) and status1_p1(7) and status1_p1(6)) = '1' then  --check top 4 bits for 3rd edge
        index_p3_latch3(1 downto 0) <= "01";
        index_p3_latch              <= index_p1_latch(6);
      elsif (k and status1_p1(5)) = '1' then
        index_p3_latch3(1 downto 0) <= "00";
        index_p3_latch              <= index_p1_latch(5);
      else
        status12_p3                 <= '0';
        index_p3_latch3(2 downto 0) <= "000";
        index_p3_latch              <= "00";
      end if;

      if (status1_n1(8) and status1_n1(7) and status1_n1(6)) = '1' then
        index_n3_latch3(1 downto 0) <= "01";
        index_n3_latch              <= index_n1_latch(6);
      elsif (l and status1_n1(5)) = '1' then
        index_n3_latch3(1 downto 0) <= "00";
        index_n3_latch              <= index_n1_latch(5);
      else
        status12_n3                 <= '0';
        index_n3_latch3(2 downto 0) <= "000";
        index_n3_latch              <= "00";
      end if;

      status11_p1 <= status1_p1(4 downto 1);
      status11_n1 <= status1_n1(4 downto 1);
      for z in 4 downto 1 loop
        index_p_low(z) <= index_p1_latch(z);
        index_n_low(z) <= index_n1_latch(z);
      end loop;

------------------------------- next bits pos 1 r & f -------------------------------------                     
      for j in 1 to 2 loop              -- 2 bit status, middle bits of pos1
        if status1_p1((j*4)) = '1' then
          index_p1_latch3(j) <= "11";
          index_p1_latch2(j) <= index_p1_latch(j*4);
        elsif status1_p1((j*4)-1) = '1' then
          index_p1_latch3(j) <= "10";
          index_p1_latch2(j) <= index_p1_latch((j*4)-1);
        elsif status1_p1((j*4)-2) = '1' then
          index_p1_latch3(j) <= "01";
          index_p1_latch2(j) <= index_p1_latch((j*4)-2);
        elsif status1_p1((j*4)-3) = '1' then
          index_p1_latch3(j) <= "00";
          index_p1_latch2(j) <= index_p1_latch((j*4)-3);
        else
          status2_p1(j)      <= '0';
          index_p1_latch2(j) <= "00";
        end if;
        
        sum2_p(j) <= conv_std_logic_vector((conv_integer(sum1_p(j*4)) +
                                            conv_integer(sum1_p((j*4)-1)) +
                                            conv_integer(sum1_p((j*4)-2)) +
                                            conv_integer(sum1_p((j*4)-3))),5);

        if status1_n1((j*4)) = '1' then
          index_n1_latch3(j) <= "11";
          index_n1_latch2(j) <= index_n1_latch(j*4);
        elsif status1_n1((j*4)-1) = '1' then
          index_n1_latch3(j) <= "10";
          index_n1_latch2(j) <= index_n1_latch((j*4)-1);
        elsif status1_n1((j*4)-2) = '1' then
          index_n1_latch3(j) <= "01";
          index_n1_latch2(j) <= index_n1_latch((j*4)-2);
        elsif status1_n1((j*4)-3) = '1' then
          index_n1_latch3(j) <= "00";
          index_n1_latch2(j) <= index_n1_latch((j*4)-3);
        else
          status2_n1(j)      <= '0';
          index_n1_latch2(j) <= "00";
        end if;

        sum2_n(j) <= conv_std_logic_vector((conv_integer(sum1_n(j*4)) +
                                            conv_integer(sum1_n((j*4)-1)) +
                                            conv_integer(sum1_n((j*4)-2)) +
                                            conv_integer(sum1_n((j*4)-3))),5);

      end loop;

------------------------------- lower 4 bits 2nd edge -------------------------------------                     
      b := dec13 (status11_p1(4 downto 2));
      x := dec13 (status11_n1(4 downto 2));

      if status2_p1(2) = '0' then       --no edge in top 4 bits, search for 2nd
        if (status11_p1(3) and status11_p1(4)) = '1' then
          index_p2_latch333(1 downto 0) := "10";
          index_p2_out                  <= index_p_low(3);
        elsif (status11_p1(2) and
               (status11_p1(3) xor status11_p1(4))) = '1' then
          index_p2_latch333(1 downto 0) := "01";
          index_p2_out                  <= index_p_low(2);
        elsif (status11_p1(1) and b) = '1' then
          index_p2_latch333(1 downto 0) := "00";
          index_p2_out                  <= index_p_low(1);
        else
          status1_p2(1)                 <= '0';
          index_p2_latch333(1 downto 0) := "00";
          index_p2_out                  <= "00";
        end if;
      elsif status2_p1(2) = '1' then    -- 1 edge in top 4 bits, search for 1st
        if status11_p1(4) = '1' then
          index_p2_latch333(1 downto 0) := "11";
          index_p2_out                  <= index_p_low(4);
        elsif status11_p1(3) = '1' then
          index_p2_latch333(1 downto 0) := "10";
          index_p2_out                  <= index_p_low(3);
        elsif status11_p1(2) = '1' then
          index_p2_latch333(1 downto 0) := "01";
          index_p2_out                  <= index_p_low(2);
        elsif status11_p1(1) = '1' then
          index_p2_latch333(1 downto 0) := "00";
          index_p2_out                  <= index_p_low(1);
        else
          status1_p2(1)                 <= '0';
          index_p2_latch333(1 downto 0) := "00";
          index_p2_out                  <= "00";
        end if;
      else
        status1_p2(1)                 <= '0';
        index_p2_latch333(1 downto 0) := "00";
        index_p2_out                  <= "00";
      end if;
      index_p2_latch33 <= index_p2_latch333;

      index_p2_latch33_1 <= index_p2_latch3;
      index_p2_out_1     <= index_p2_latch;

      if status2_n1(2) = '0' then
        if (status11_n1(3) and status11_n1(4)) = '1' then
          index_n2_latch333(1 downto 0) := "10";
          index_n2_out                  <= index_n_low(3);
        elsif (status11_n1(2) and
               (status11_n1(3) xor status11_n1(4))) = '1' then
          index_n2_latch333(1 downto 0) := "01";
          index_n2_out                  <= index_n_low(2);
        elsif (status11_n1(1) and x) = '1' then
          index_n2_latch333(1 downto 0) := "00";
          index_n2_out                  <= index_n_low(1);
        else
          status1_n2(1)                 <= '0';
          index_n2_latch333(1 downto 0) := "00";
          index_n2_out                  <= "00";
        end if;
      elsif status2_n1(2) = '1' then
        if status11_n1(4) = '1' then
          index_n2_latch333(1 downto 0) := "11";
          index_n2_out                  <= index_n_low(4);
        elsif status11_n1(3) = '1' then
          index_n2_latch333(1 downto 0) := "10";
          index_n2_out                  <= index_n_low(3);
        elsif status11_n1(2) = '1' then
          index_n2_latch333(1 downto 0) := "01";
          index_n2_out                  <= index_n_low(2);
        elsif status11_n1(1) = '1' then
          index_n2_latch333(1 downto 0) := "00";
          index_n2_out                  <= index_n_low(1);
        else
          status1_n2(1)                 <= '0';
          index_n2_latch333(1 downto 0) := "00";
          index_n2_out                  <= "00";
        end if;
      else
        status1_n2(1)                 <= '0';
        index_n2_latch333(1 downto 0) := "00";
        index_n2_out                  <= "00";
      end if;
      index_n2_latch33 <= index_n2_latch333;

      index_n2_latch33_1 <= index_n2_latch3;
      index_n2_out_1     <= index_n2_latch;

      status1_p2(2) <= status12_p2;
      status1_n2(2) <= status12_n2;

--------------------------------- lower 4 bits 3rd edge -------------------------------------                   
      m := dec23 (status11_p1(4 downto 2));
      n := dec23 (status11_n1(4 downto 2));

      if status2_p1(2) = '1' then       --1 edge in top 4 bits, search for 2nd
        if (status11_p1(3) and status11_p1(4)) = '1' then
          index_p3_latch333(1 downto 0) := "10";
          index_p3_out                  <= index_p_low(3);
        elsif (status11_p1(2) and
               (status11_p1(3) xor status11_p1(4))) = '1' then
          index_p3_latch333(1 downto 0) := "01";
          index_p3_out                  <= index_p_low(2);
        elsif (status11_p1(1) and b) = '1' then
          index_p3_latch333(1 downto 0) := "00";
          index_p3_out                  <= index_p_low(1);
        else
          status1_p3(1)                 <= '0';
          index_p3_latch333(1 downto 0) := "00";
          index_p3_out                  <= "00";
        end if;
      elsif status12_p2 = '1' then  --2 edges in top 4 bits, search for 1st 
        if status11_p1(4) = '1' then
          index_p3_latch333(1 downto 0) := "11";
          index_p3_out                  <= index_p_low(4);
        elsif status11_p1(3) = '1' then
          index_p3_latch333(1 downto 0) := "10";
          index_p3_out                  <= index_p_low(3);
        elsif status11_p1(2) = '1' then
          index_p3_latch333(1 downto 0) := "01";
          index_p3_out                  <= index_p_low(2);
        elsif status11_p1(1) = '1' then
          index_p3_latch333(1 downto 0) := "00";
          index_p3_out                  <= index_p_low(1);
        else
          status1_p3(1)                 <= '0';
          index_p3_latch333(1 downto 0) := "00";
          index_p3_out                  <= "00";
        end if;
      else                          --no edges in top 4 bits, search for 3rd
        if (status11_p1(4) and status11_p1(3) and status11_p1(2)) = '1' then
          index_p3_latch333(1 downto 0) := "01";
          index_p3_out                  <= index_p_low(2);
        elsif (m and status11_p1(1)) = '1' then
          index_p3_latch333(1 downto 0) := "00";
          index_p3_out                  <= index_p_low(1);
        else
          status1_p3(1)                 <= '0';
          index_p3_latch333(1 downto 0) := "00";
          index_p3_out                  <= "00";
        end if;
      end if;
      index_p3_latch33 <= index_p3_latch333;

      index_p3_latch33_1 <= index_p3_latch3;
      index_p3_out_1     <= index_p3_latch;

      if status2_n1(2) = '1' then       --1 edge in top 4 bits, search for 2nd
        if (status11_n1(3) and status11_n1(4)) = '1' then
          index_n3_latch333(1 downto 0) := "10";
          index_n3_out                  <= index_n_low(3);
        elsif (status11_n1(2) and
               (status11_n1(3) xor status11_n1(4))) = '1' then
          index_n3_latch333(1 downto 0) := "01";
          index_n3_out                  <= index_n_low(2);
        elsif (status11_n1(1) and x) = '1' then
          index_n3_latch333(1 downto 0) := "00";
          index_n3_out                  <= index_n_low(1);
        else
          status1_n3(1)                 <= '0';
          index_n3_latch333(1 downto 0) := "00";
          index_n3_out                  <= "00";
        end if;
      elsif status12_n2 = '1' then  --2 edges in top 4 bits, search for 1st 
        if status11_n1(4) = '1' then
          index_n3_latch333(1 downto 0) := "11";
          index_n3_out                  <= index_n_low(4);
        elsif status11_n1(3) = '1' then
          index_n3_latch333(1 downto 0) := "10";
          index_n3_out                  <= index_n_low(3);
        elsif status11_n1(2) = '1' then
          index_n3_latch333(1 downto 0) := "01";
          index_n3_out                  <= index_n_low(2);
        elsif status11_n1(1) = '1' then
          index_n3_latch333(1 downto 0) := "00";
          index_n3_out                  <= index_n_low(1);
        else
          status1_n3(1)                 <= '0';
          index_n3_latch333(1 downto 0) := "00";
          index_n3_out                  <= "00";
        end if;
      else                          --no edges in top 4 bits, search for 3rd
        if (status11_n1(4) and status11_n1(3) and status11_n1(2)) = '1' then
          index_n3_latch333(1 downto 0) := "01";
          index_n3_out                  <= index_n_low(2);
        elsif (n and status11_p1(1)) = '1' then
          index_n3_latch333(1 downto 0) := "00";
          index_n3_out                  <= index_n_low(1);
        else
          status1_n3(1)                 <= '0';
          index_n3_latch333(1 downto 0) := "00";
          index_n3_out                  <= "00";
        end if;
      end if;
      index_n3_latch33 <= index_n3_latch333;

      index_n3_latch33_1 <= index_n3_latch3;
      index_n3_out_1     <= index_n3_latch;

      status1_p3(2) <= status12_p3;
      status1_n3(2) <= status12_n3;

------------------------------- status, MSB pos1 -------------------------------------                  
      if status2_p1(2) = '1' then       --final status flag pos1
        index_p1_latch4  <= '1';
        index_p1_latch22 <= index_p1_latch2(2);
        index_p1_latch33 <= index_p1_latch3(2);
      elsif status2_p1(1) = '1' then
        index_p1_latch4  <= '0';
        index_p1_latch22 <= index_p1_latch2(1);
        index_p1_latch33 <= index_p1_latch3(1);
      else
        status_i_p1      <= '0';
        index_p1_latch22 <= "00";
        index_p1_latch33 <= "00";
        index_p1_latch4  <= '0';
      end if;

      sum_p <= conv_std_logic_vector((conv_integer(sum2_p(1)) + conv_integer(sum2_p(2))), 6);

      if status2_n1(2) = '1' then
        index_n1_latch4  <= '1';
        index_n1_latch22 <= index_n1_latch2(2);
        index_n1_latch33 <= index_n1_latch3(2);
      elsif status2_n1(1) = '1' then
        index_n1_latch4  <= '0';
        index_n1_latch22 <= index_n1_latch2(1);
        index_n1_latch33 <= index_n1_latch3(1);
      else
        status_i_n1      <= '0';
        index_n1_latch22 <= "00";
        index_n1_latch33 <= "00";
        index_n1_latch4  <= '0';
      end if;

      sum_n <= conv_std_logic_vector((conv_integer(sum2_n(1)) + conv_integer(sum2_n(2))), 6);

------------------------------- output assignments -------------------------------------                
      STATUS_P1_i <= status_i_p1;
      EDGE_RIS1_i <= index_p1_latch4 & index_p1_latch33 & index_p1_latch22;

      STATUS_P2_i <= status1_p2(2) or status1_p2(1);
      if status1_p2(2) = '1' then  -- take values from upper or lower half of status1
        EDGE_RIS2_i <= index_p2_latch33_1 & index_p2_out_1;
      else
        EDGE_RIS2_i <= '0' & index_p2_latch33 & index_p2_out;
      end if;

      STATUS_P3_i <= status1_p3(2) or status1_p3(1);
      if status1_p3(2) = '1' then
        EDGE_RIS3_i <= index_p3_latch33_1 & index_p3_out_1;
      else
        EDGE_RIS3_i <= '0' & index_p3_latch33 & index_p3_out;
      end if;

      SUM_RIS_i <= sum_p;

      STATUS_N1_i <= status_i_n1;
      EDGE_FAL1_i <= index_n1_latch4 & index_n1_latch33 & index_n1_latch22;

      STATUS_N2_i <= status1_n2(2) or status1_n2(1);
      if status1_n2(2) = '1' then
        EDGE_FAL2_i <= index_n2_latch33_1 & index_n2_out_1;
      else
        EDGE_FAL2_i <= '0' & index_n2_latch33 & index_n2_out;
      end if;

      STATUS_N3_i <= status1_n3(2) or status1_n3(1);
      if status1_n3(2) = '1' then
        EDGE_FAL3_i <= index_n3_latch33_1 & index_n3_out_1;
      else
        EDGE_FAL3_i <= '0' & index_n3_latch33 & index_n3_out;
      end if;

      SUM_FAL_i <= sum_n;


      SUM_RIS <= SUM_RIS_i;
      SUM_FAL <= SUM_FAL_i;

      if STATUS_N2_i = '1' then
        if EDGE_RIS2_i < EDGE_RIS1_i then
          EDGE_FAL1 <= EDGE_RIS1_i+2;
          EDGE_FAL2 <= EDGE_RIS2_i+2;
        else
          EDGE_FAL1 <= EDGE_RIS2_i+2;
          EDGE_FAL2 <= EDGE_RIS1_i+2;
        end if;
        STATUS_P1 <= STATUS_N2_i;
        if STATUS_P2_i = '0' then
          STATUS_P2 <= '0';
        else
          STATUS_P2 <= STATUS_N1_i;
        end if;
        
      else
        
        if STATUS_P1_i = '1' then
          EDGE_FAL1 <= EDGE_RIS1_i+2;
          STATUS_N1 <= STATUS_P1_i;
        else
          EDGE_FAL1 <= (others => '0');
          STATUS_N1 <= '0';
        end if;
        STATUS_N2 <= '0';
        EDGE_FAL2 <= (others => '0');

        if STATUS_P2_i = '1' then
          STATUS_P1 <= '1';
        else
          STATUS_P1 <= '0';
        end if;
        
      end if;


      if STATUS_P2_i = '1' then
        if EDGE_FAL2_i < EDGE_FAL1_i then
          EDGE_RIS1 <= EDGE_FAL1_i-1;
          EDGE_RIS2 <= EDGE_FAL2_i-1;
        else
          EDGE_RIS1 <= EDGE_FAL2_i-1;
          EDGE_RIS2 <= EDGE_FAL1_i-1;
        end if;
        STATUS_N1 <= STATUS_P2_i;
        if STATUS_N2_i = '0' then
          STATUS_N2 <= '0';
        else
          STATUS_N2 <= STATUS_P1_i;
        end if;
        
      else
        
        if STATUS_N1_i = '1' then
          EDGE_RIS1 <= EDGE_FAL1_i-1;
          STATUS_P1 <= STATUS_N1_i;
        else
          EDGE_RIS1 <= (others => '0');
          STATUS_P1 <= '0';
        end if;
        STATUS_P2 <= '0';
        EDGE_RIS2 <= (others => '0');

        if STATUS_N2_i = '0' then
          STATUS_N1 <= '1';
        else
          STATUS_N1 <= '0';
        end if;
      end if;

      EDGE_FAL3 <= (others => '0');
      EDGE_RIS3 <= (others => '0');
      STATUS_P3 <= '0';
      STATUS_N3 <= '0';

    end if;
  end process;
end new2;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:04 2008 for BCM-AAA by  1.5.7.1-20081012