BCM-AAA: rios_all.vhd Source File

00001 --**************************************************************
00002 --*                                                            *
00003 --*     The source code for the ATLAS BCM "AAA" FPGA is made   *
00004 --*     available via the GNU General Public License (GPL)     *
00005 --*     unless otherwise stated below.                         *
00006 --*                                                            *
00007 --*     In case of problems/questions/bug reports etc. please  *
00008 --*     contact michael.niegl@cern.ch                          *
00009 --*                                                            *
00010 --**************************************************************
00011 
00012 --**************************************************************
00013 --*                                                            *
00014 --*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/rio/rios_all.vhd,v $ 
00015 --*  $Revision: 1.22.2.4 $                                         *
00016 --*  $Name: dev $                                              *
00017 --*  $Author: mniegl $                                         *
00018 --*  $Date: 2008/11/03 17:57:48 $                              *
00019 
00020 
00021 --*                                                            *
00022 --**************************************************************
00023 
00024 
00025 library ieee;
00026 
00027 use ieee.std_logic_1164.all;
00028 
00029 use ieee.std_logic_arith.all;
00030 
00031 use ieee.std_logic_unsigned.all;
00032 
00033 library unisim;
00034 
00035 use unisim.vcomponents.all;
00036 library work;
00037 use work.main_components.all;
00038 
00039 
00040 entity rios_all is
00041   port (
00042     BCLK                 : in  std_logic;
00043     BCLK4X               : in  std_logic;
00044     RIOCLK_1             : in  std_logic;
00045     RIOCLK_2             : in  std_logic;
00046     BCLK2X               : in  std_logic;
00047     EN                   : in  std_logic;
00048     RESET                : in  std_logic;
00049     SEP_RESET            : in  std_logic_vector(7 downto 0);
00050     CALIBRATE_RIOS       : in  std_logic;
00051     LOCK_OUT             : out std_logic;
00052     RIOS_READY           : out std_logic;
00053     DONE                 : out std_logic;
00054     CHECK                : out std_logic;
00055     RXN_C_IE             : in  std_logic_vector(1 downto 0);
00056     RXP_C_IE             : in  std_logic_vector(1 downto 0);
00057     TXN_C_IE             : out std_logic_vector(1 downto 0);
00058     TXP_C_IE             : out std_logic_vector(1 downto 0);
00059     RXN_C_AH             : in  std_logic_vector(1 downto 0);
00060     RXP_C_AH             : in  std_logic_vector(1 downto 0);
00061     TXN_C_AH             : out std_logic_vector(1 downto 0);
00062     TXP_C_AH             : out std_logic_vector(1 downto 0);
00063     RXN_A_WM             : in  std_logic_vector(1 downto 0);
00064     RXP_A_WM             : in  std_logic_vector(1 downto 0);
00065     TXN_A_WM             : out std_logic_vector(1 downto 0);
00066     TXP_A_WM             : out std_logic_vector(1 downto 0);
00067     RXN_A_HH             : in  std_logic_vector(1 downto 0);
00068     RXP_A_HH             : in  std_logic_vector(1 downto 0);
00069     TXN_A_HH             : out std_logic_vector(1 downto 0);
00070     TXP_A_HH             : out std_logic_vector(1 downto 0);
00071     CAL_IRENA            : in  std_logic;
00072     CAL_EWA              : in  std_logic;
00073     CAL_ANDREJ           : in  std_logic;
00074     CAL_HEINZ            : in  std_logic;
00075     CAL_MARKO            : in  std_logic;
00076     CAL_WILLIAM          : in  std_logic;
00077     CAL_HARRIS           : in  std_logic;
00078     CAL_HELMUT           : in  std_logic;
00079     MASK_IRENA           : out std_logic;
00080     MASK_EWA             : out std_logic;
00081     MASK_ANDREJ          : out std_logic;
00082     MASK_HEINZ           : out std_logic;
00083     MASK_MARKO           : out std_logic;
00084     MASK_WILLIAM         : out std_logic;
00085     MASK_HARRIS          : out std_logic;
00086     MASK_HELMUT          : out std_logic;
00087     RX_LOCK1             : out std_logic;
00088     RX_LOCK2             : out std_logic;
00089     RX_LOCK3             : out std_logic;
00090     RX_LOCK4             : out std_logic;
00091     RX_LOCK5             : out std_logic;
00092     RX_LOCK6             : out std_logic;
00093     RX_LOCK7             : out std_logic;
00094     RX_LOCK8             : out std_logic;
00095     TX_LOCK1             : out std_logic;
00096     TX_LOCK2             : out std_logic;
00097     TX_LOCK3             : out std_logic;
00098     TX_LOCK4             : out std_logic;
00099     TX_LOCK5             : out std_logic;
00100     TX_LOCK6             : out std_logic;
00101     TX_LOCK7             : out std_logic;
00102     TX_LOCK8             : out std_logic;
00103     RX_READY1            : out std_logic;
00104     RX_READY2            : out std_logic;
00105     RX_READY3            : out std_logic;
00106     RX_READY4            : out std_logic;
00107     RX_READY5            : out std_logic;
00108     RX_READY6            : out std_logic;
00109     RX_READY7            : out std_logic;
00110     RX_READY8            : out std_logic;
00111     TX_READY1            : out std_logic;
00112     TX_READY2            : out std_logic;
00113     TX_READY3            : out std_logic;
00114     TX_READY4            : out std_logic;
00115     TX_READY5            : out std_logic;
00116     TX_READY6            : out std_logic;
00117     TX_READY7            : out std_logic;
00118     TX_READY8            : out std_logic;
00119     MULT_IRENA           : out std_logic_vector(7 downto 0);
00120     MULT_EWA             : out std_logic_vector(7 downto 0);
00121     MULT_ANDREJ          : out std_logic_vector(7 downto 0);
00122     MULT_HEINZ           : out std_logic_vector(7 downto 0);
00123     MULT_MARKO           : out std_logic_vector(7 downto 0);
00124     MULT_WILLIAM         : out std_logic_vector(7 downto 0);
00125     MULT_HARRIS          : out std_logic_vector(7 downto 0);
00126     MULT_HELMUT          : out std_logic_vector(7 downto 0);
00127     PROC_DATA            : out std_logic_vector(191 downto 0);
00128     RAW_DATA             : out std_logic_vector(255 downto 0);
00129     ADJUST_TIME_IRENA    : in  integer range 0 to 32;
00130     ADJUST_TIME_EWA      : in  integer range 0 to 32;
00131     ADJUST_TIME_ANDREJ   : in  integer range 0 to 32;
00132     ADJUST_TIME_HEINZ    : in  integer range 0 to 32;
00133     ADJUST_TIME_MARKO    : in  integer range 0 to 32;
00134     ADJUST_TIME_WILLIAM  : in  integer range 0 to 32;
00135     ADJUST_TIME_HARRIS   : in  integer range 0 to 32;
00136     ADJUST_TIME_HELMUT   : in  integer range 0 to 32;
00137     ADJUST_TIME_IRENA2   : in  integer range 0 to 32;
00138     ADJUST_TIME_EWA2     : in  integer range 0 to 32;
00139     ADJUST_TIME_ANDREJ2  : in  integer range 0 to 32;
00140     ADJUST_TIME_HEINZ2   : in  integer range 0 to 32;
00141     ADJUST_TIME_MARKO2   : in  integer range 0 to 32;
00142     ADJUST_TIME_WILLIAM2 : in  integer range 0 to 32;
00143     ADJUST_TIME_HARRIS2  : in  integer range 0 to 32;
00144     ADJUST_TIME_HELMUT2  : in  integer range 0 to 32;
00145     COARSE_TIME_IRENA    : in  std_logic_vector(7 downto 0);
00146     COARSE_TIME_EWA      : in  std_logic_vector(7 downto 0);
00147     COARSE_TIME_ANDREJ   : in  std_logic_vector(7 downto 0);
00148     COARSE_TIME_HEINZ    : in  std_logic_vector(7 downto 0);
00149     COARSE_TIME_MARKO    : in  std_logic_vector(7 downto 0);
00150     COARSE_TIME_WILLIAM  : in  std_logic_vector(7 downto 0);
00151     COARSE_TIME_HARRIS   : in  std_logic_vector(7 downto 0);
00152     COARSE_TIME_HELMUT   : in  std_logic_vector(7 downto 0)
00153     );
00154 end rios_all;
00155 
00156 
00157 architecture rios_all_arc of rios_all is
00158 
00159 --*************************** Signal Declarations *****************************
00160   signal done1          : std_logic                     := '0';
00161   signal done2          : std_logic                     := '0';
00162   signal readya1        : std_logic                     := '0';
00163   signal readya2        : std_logic                     := '0';
00164   signal readya3        : std_logic                     := '0';
00165   signal readya4        : std_logic                     := '0';
00166   signal readyc1        : std_logic                     := '0';
00167   signal readyc2        : std_logic                     := '0';
00168   signal readyc3        : std_logic                     := '0';
00169   signal readyc4        : std_logic                     := '0';
00170   signal check1         : std_logic                     := '0';
00171   signal check2         : std_logic                     := '0';
00172   signal check3         : std_logic                     := '0';
00173   signal check4         : std_logic                     := '0';
00174   signal check5         : std_logic                     := '0';
00175   signal check6         : std_logic                     := '0';
00176   signal check7         : std_logic                     := '0';
00177   signal check8         : std_logic                     := '0';
00178   signal irena_1        : std_logic                     := '0';
00179   signal irena_2        : std_logic                     := '0';
00180   signal ewa_1          : std_logic                     := '0';
00181   signal ewa_2          : std_logic                     := '0';
00182   signal andrej_1       : std_logic                     := '0';
00183   signal andrej_2       : std_logic                     := '0';
00184   signal heinz_1        : std_logic                     := '0';
00185   signal heinz_2        : std_logic                     := '0';
00186   signal marko_1        : std_logic                     := '0';
00187   signal marko_2        : std_logic                     := '0';
00188   signal william_1      : std_logic                     := '0';
00189   signal william_2      : std_logic                     := '0';
00190   signal harris_1       : std_logic                     := '0';
00191   signal harris_2       : std_logic                     := '0';
00192   signal helmut_1       : std_logic                     := '0';
00193   signal helmut_2       : std_logic                     := '0';
00194   signal t1_irena_i     : std_logic_vector(7 downto 0)  := (others => '0');
00195   signal t2_irena_i     : std_logic_vector(7 downto 0)  := (others => '0');
00196   signal w1_irena_i     : std_logic_vector(7 downto 0)  := (others => '0');
00197   signal w2_irena_i     : std_logic_vector(7 downto 0)  := (others => '0');
00198   signal t1_ewa_i       : std_logic_vector(7 downto 0)  := (others => '0');
00199   signal t2_ewa_i       : std_logic_vector(7 downto 0)  := (others => '0');
00200   signal w1_ewa_i       : std_logic_vector(7 downto 0)  := (others => '0');
00201   signal w2_ewa_i       : std_logic_vector(7 downto 0)  := (others => '0');
00202   signal t1_andrej_i    : std_logic_vector(7 downto 0)  := (others => '0');
00203   signal t2_andrej_i    : std_logic_vector(7 downto 0)  := (others => '0');
00204   signal w1_andrej_i    : std_logic_vector(7 downto 0)  := (others => '0');
00205   signal w2_andrej_i    : std_logic_vector(7 downto 0)  := (others => '0');
00206   signal t1_heinz_i     : std_logic_vector(7 downto 0)  := (others => '0');
00207   signal t2_heinz_i     : std_logic_vector(7 downto 0)  := (others => '0');
00208   signal w1_heinz_i     : std_logic_vector(7 downto 0)  := (others => '0');
00209   signal w2_heinz_i     : std_logic_vector(7 downto 0)  := (others => '0');
00210   signal t1_marko_i     : std_logic_vector(7 downto 0)  := (others => '0');
00211   signal t2_marko_i     : std_logic_vector(7 downto 0)  := (others => '0');
00212   signal w1_marko_i     : std_logic_vector(7 downto 0)  := (others => '0');
00213   signal w2_marko_i     : std_logic_vector(7 downto 0)  := (others => '0');
00214   signal t1_william_i   : std_logic_vector(7 downto 0)  := (others => '0');
00215   signal t2_william_i   : std_logic_vector(7 downto 0)  := (others => '0');
00216   signal w1_william_i   : std_logic_vector(7 downto 0)  := (others => '0');
00217   signal w2_william_i   : std_logic_vector(7 downto 0)  := (others => '0');
00218   signal t1_harris_i    : std_logic_vector(7 downto 0)  := (others => '0');
00219   signal t2_harris_i    : std_logic_vector(7 downto 0)  := (others => '0');
00220   signal w1_harris_i    : std_logic_vector(7 downto 0)  := (others => '0');
00221   signal w2_harris_i    : std_logic_vector(7 downto 0)  := (others => '0');
00222   signal t1_helmut_i    : std_logic_vector(7 downto 0)  := (others => '0');
00223   signal t2_helmut_i    : std_logic_vector(7 downto 0)  := (others => '0');
00224   signal w1_helmut_i    : std_logic_vector(7 downto 0)  := (others => '0');
00225   signal w2_helmut_i    : std_logic_vector(7 downto 0)  := (others => '0');
00226   signal raw_irena      : std_logic_vector(31 downto 0) := (others => '0');
00227   signal raw_ewa        : std_logic_vector(31 downto 0) := (others => '0');
00228   signal raw_andrej     : std_logic_vector(31 downto 0) := (others => '0');
00229   signal raw_heinz      : std_logic_vector(31 downto 0) := (others => '0');
00230   signal raw_marko      : std_logic_vector(31 downto 0) := (others => '0');
00231   signal raw_william    : std_logic_vector(31 downto 0) := (others => '0');
00232   signal raw_harris     : std_logic_vector(31 downto 0) := (others => '0');
00233   signal raw_helmut     : std_logic_vector(31 downto 0) := (others => '0');
00234   signal mult_irena_i   : std_logic_vector(7 downto 0)  := (others => '0');
00235   signal mult_ewa_i     : std_logic_vector(7 downto 0)  := (others => '0');
00236   signal mult_andrej_i  : std_logic_vector(7 downto 0)  := (others => '0');
00237   signal mult_heinz_i   : std_logic_vector(7 downto 0)  := (others => '0');
00238   signal mult_marko_i   : std_logic_vector(7 downto 0)  := (others => '0');
00239   signal mult_william_i : std_logic_vector(7 downto 0)  := (others => '0');
00240   signal mult_harris_i  : std_logic_vector(7 downto 0)  := (others => '0');
00241   signal mult_helmut_i  : std_logic_vector(7 downto 0)  := (others => '0');
00242 
00243 
00244   constant XOR_PAT : std_logic_vector(31 downto 0) := x"cccc_cccc";
00245 
00246 --*************************************************************************
00247 --*                               main code
00248 --*************************************************************************
00249 begin
00250 
00251   DONE       <= done1 and done2;
00252   RIOS_READY <= readya1 and readya2 and readya3 and readya4 and readyc1 and readyc2 and readyc3 and readyc4;
00253   RX_READY1  <= readyc1;
00254   RX_READY2  <= readyc1;
00255   RX_READY3  <= readyc3;
00256   RX_READY4  <= readyc3;
00257   RX_READY5  <= readya1;
00258   RX_READY6  <= readya1;
00259   RX_READY7  <= readya3;
00260   RX_READY8  <= readya3;
00261   TX_READY1  <= readyc2;
00262   TX_READY2  <= readyc2;
00263   TX_READY3  <= readyc4;
00264   TX_READY4  <= readyc4;
00265   TX_READY5  <= readya2;
00266   TX_READY6  <= readya2;
00267   TX_READY7  <= readya4;
00268   TX_READY8  <= readya4;
00269   CHECK      <= check1 and check2 and check3 and check4 and check5 and check6 and check7 and check8;
00270   LOCK_OUT   <= '1';                    -- for later use
00271 
00272 
00273   PROC_DATA <= ewa_1 & t1_ewa_i(5 downto 0) & w1_ewa_i(4 downto 0) & ewa_2 & t2_ewa_i(5 downto 0) & w2_ewa_i(4 downto 0) &
00274                irena_1 & t1_irena_i(5 downto 0) & w1_irena_i(4 downto 0) & irena_2 & t2_irena_i(5 downto 0) & w2_irena_i(4 downto 0) &
00275                heinz_1 & t1_heinz_i(5 downto 0) & w1_heinz_i(4 downto 0) & heinz_2 & t2_heinz_i(5 downto 0) & w2_heinz_i(4 downto 0) &
00276                andrej_1 & t1_andrej_i(5 downto 0) & w1_andrej_i(4 downto 0) & andrej_2 & t2_andrej_i(5 downto 0) & w2_andrej_i(4 downto 0) &
00277                william_1 & t1_william_i(5 downto 0) & w1_william_i(4 downto 0) & william_2 & t2_william_i(5 downto 0) & w2_william_i(4 downto 0) &
00278                marko_1 & t1_marko_i(5 downto 0) & w1_marko_i(4 downto 0) & marko_2 & t2_marko_i(5 downto 0) & w2_marko_i(4 downto 0) &
00279                helmut_1 & t1_helmut_i(5 downto 0) & w1_helmut_i(4 downto 0) & helmut_2 & t2_helmut_i(5 downto 0) & w2_helmut_i(4 downto 0) &
00280                harris_1 & t1_harris_i(5 downto 0) & w1_harris_i(4 downto 0) & harris_2 & t2_harris_i(5 downto 0) & w2_harris_i(4 downto 0);  -- when rising_edge(BCLK);
00281 
00282 --*     PROC_DATA <= 191 irena_1 & t1_irena_i(5 downto 0) 190-185 & w1_irena_i(4 downto 0) 184-180 & irena_2 179 & t2_irena_i(5 downto 0) 178-173 & w1_irena_i(4 downto 0) & 172-168
00283 --*                  167 ewa_1 & t1_ewa_i(5 downto 0) 166-161 & w1_ewa_i(4 downto 0) 160-156 & ewa_2 155 & t2_ewa_i(5 downto 0) 154-149 & w2_ewa_i(4 downto 0) & 148-144
00284 --*                  143 andrej_1 & t1_andrej_i(5 downto 0) 142-137 & w1_andrej_i(4 downto 0) 136-132 & andrej_2 131 & t2_andrej_i(5 downto 0) 130-125 & w2_andrej_i(4 downto 0) & 124-120
00285 --*                  119 heinz_1 & t1_heinz_i(5 downto 0) 118-113 & w1_heinz_i(4 downto 0) 112-108 & heinz_2 107 & t2_heinz_i(5 downto 0) 106-101 & w2_heinz_i(4 downto 0) & 100-96
00286 --*                   95 marko_1 & t1_marko_i(5 downto 0) 94-89 & w1_marko_i(4 downto 0) 88-84 & marko_2 83 & t2_marko_i(5 downto 0) 82-77 & w2_marko_i(4 downto 0) & 76-72
00287 --*                   71 william_1 & t1_william_i(5 downto 0) 70-65 & w1_william_i(4 downto 0) 64-60 & william_2 59 & t2_william_i(5 downto 0) 58-53 & w2_william_i(4 downto 0) & 52-48
00288 --*                   47 harris_1 & t1_harris_i(5 downto 0) 46-41 & w1_harris_i(4 downto 0) 40-36 & harris_2 35 & t2_harris_i(5 downto 0) 34-29 & w2_harris_i(4 downto 0) & 28-24
00289 --*                   23 helmut_1 & t1_helmut_i(5 downto 0) 22-17 & w1_helmut_i(4 downto 0) 16-12 & helmut_2 11 & t2_helmut_i(5 downto 0) 10-5 & w2_helmut_i(4 downto 0) 4-0
00290   
00291   RAW_DATA <= raw_ewa & raw_irena & raw_heinz & raw_andrej & raw_william & raw_marko & raw_helmut & raw_harris;  -- when rising_edge(BCLK2X);
00292 
00293   MULT_IRENA   <= mult_irena_i;         -- when rising_edge(BCLK);
00294   MULT_EWA     <= mult_ewa_i;           --when rising_edge(BCLK);
00295   MULT_ANDREJ  <= mult_andrej_i;        --when rising_edge(BCLK);
00296   MULT_HEINZ   <= mult_heinz_i;         --when rising_edge(BCLK);
00297   MULT_MARKO   <= mult_marko_i;         --when rising_edge(BCLK);
00298   MULT_WILLIAM <= mult_william_i;       --when rising_edge(BCLK);
00299   MULT_HARRIS  <= mult_harris_i;        --when rising_edge(BCLK);
00300   MULT_HELMUT  <= mult_helmut_i;        --when rising_edge(BCLK);
00301 
00302 
00303   side_a : side_4rios
00304     generic map (
00305       PATTERN => XOR_PAT)
00306     port map
00307     (
00308       BCLK                => BCLK,
00309       BCLK2X              => BCLK2X,
00310       BCLK4X              => BCLK4X,
00311       RIOCLK_1            => RIOCLK_1,
00312       RIOCLK_2            => RIOCLK_2,
00313       SET_SHIFT_1         => "00000000",
00314       SET_SHIFT_2         => "00000000",
00315       EN                  => EN,
00316       CAL                 => CALIBRATE_RIOS,
00317       CHECK_IRENA         => check1,
00318       CHECK_EWA           => check2,
00319       CHECK_ANDREJ        => check3,
00320       CHECK_HEINZ         => check4,
00321       RES                 => RESET,
00322       SEP_RES             => SEP_RESET(7 downto 4),
00323       TX_SYSTEM_RESET_IN  => '0',
00324       RX_SYSTEM_RESET_IN  => '0',
00325       RXLOCK_OUT_IRENA    => RX_LOCK6,
00326       TXLOCK_OUT_IRENA    => TX_LOCK6,
00327       RXLOCK_OUT_EWA      => RX_LOCK5,
00328       TXLOCK_OUT_EWA      => TX_LOCK5,
00329       RXLOCK_OUT_ANDREJ   => RX_LOCK8,
00330       TXLOCK_OUT_ANDREJ   => TX_LOCK8,
00331       RXLOCK_OUT_HEINZ    => RX_LOCK7,
00332       TXLOCK_OUT_HEINZ    => TX_LOCK7,
00333       RX1N_IN_IE          => RXN_A_WM,
00334       RX1P_IN_IE          => RXP_A_WM,
00335       TX1N_OUT_IE         => TXN_A_WM,
00336       TX1P_OUT_IE         => TXP_A_WM,
00337       RX1N_IN_AH          => RXN_A_HH,
00338       RX1P_IN_AH          => RXP_A_HH,
00339       TX1N_OUT_AH         => TXN_A_HH,
00340       TX1P_OUT_AH         => TXP_A_HH,
00341       RX_READY_FLAG_IE    => readya1,
00342       TX_READY_FLAG_IE    => readya2,
00343       RX_READY_FLAG_AH    => readya3,
00344       TX_READY_FLAG_AH    => readya4,
00345       SUM_RIS_IRENA       => mult_marko_i,
00346       SUM_FAL_IRENA       => open,
00347       T1_IRENA            => t1_marko_i,
00348       T2_IRENA            => t2_marko_i,
00349       T3_IRENA            => open,
00350       W1_IRENA            => w1_marko_i,
00351       W2_IRENA            => w2_marko_i,
00352       W3_IRENA            => open,
00353       STATUS_T1_IRENA     => marko_1,
00354       STATUS_T2_IRENA     => marko_2,
00355       STATUS_T3_IRENA     => open,
00356       STATUS_W1_IRENA     => open,
00357       STATUS_W2_IRENA     => open,
00358       STATUS_W3_IRENA     => open,
00359       OVERFLOW_IRENA      => open,
00360       SUM_RIS_EWA         => mult_william_i,
00361       SUM_FAL_EWA         => open,
00362       T1_EWA              => t1_william_i,
00363       T2_EWA              => t2_william_i,
00364       T3_EWA              => open,
00365       W1_EWA              => w1_william_i,
00366       W2_EWA              => w2_william_i,
00367       W3_EWA              => open,
00368       STATUS_T1_EWA       => william_1,
00369       STATUS_T2_EWA       => william_2,
00370       STATUS_T3_EWA       => open,
00371       STATUS_W1_EWA       => open,
00372       STATUS_W2_EWA       => open,
00373       STATUS_W3_EWA       => open,
00374       OVERFLOW_EWA        => open,
00375       SUM_RIS_ANDREJ      => mult_harris_i,
00376       SUM_FAL_ANDREJ      => open,
00377       T1_ANDREJ           => t1_harris_i,
00378       T2_ANDREJ           => t2_harris_i,
00379       T3_ANDREJ           => open,
00380       W1_ANDREJ           => w1_harris_i,
00381       W2_ANDREJ           => w2_harris_i,
00382       W3_ANDREJ           => open,
00383       STATUS_T1_ANDREJ    => harris_1,
00384       STATUS_T2_ANDREJ    => harris_2,
00385       STATUS_T3_ANDREJ    => open,
00386       STATUS_W1_ANDREJ    => open,
00387       STATUS_W2_ANDREJ    => open,
00388       STATUS_W3_ANDREJ    => open,
00389       OVERFLOW_ANDREJ     => open,
00390       SUM_RIS_HEINZ       => mult_helmut_i,
00391       SUM_FAL_HEINZ       => open,
00392       T1_HEINZ            => t1_helmut_i,
00393       T2_HEINZ            => t2_helmut_i,
00394       T3_HEINZ            => open,
00395       W1_HEINZ            => w1_helmut_i,
00396       W2_HEINZ            => w2_helmut_i,
00397       W3_HEINZ            => open,
00398       STATUS_T1_HEINZ     => helmut_1,
00399       STATUS_T2_HEINZ     => helmut_2,
00400       STATUS_T3_HEINZ     => open,
00401       STATUS_W1_HEINZ     => open,
00402       STATUS_W2_HEINZ     => open,
00403       STATUS_W3_HEINZ     => open,
00404       OVERFLOW_HEINZ      => open,
00405       MASK_IRENA          => MASK_WILLIAM,
00406       MASK_EWA            => MASK_MARKO,
00407       MASK_ANDREJ         => MASK_HARRIS,
00408       MASK_HEINZ          => MASK_HELMUT,
00409       CAL_IRENA           => CAL_WILLIAM,
00410       CAL_EWA             => CAL_MARKO,
00411       CAL_ANDREJ          => CAL_HARRIS,
00412       CAL_HEINZ           => CAL_HELMUT,
00413       CAL_DONE            => done1,
00414       RAW_DATA_IRENA      => raw_william,
00415       RAW_DATA_EWA        => raw_marko,
00416       RAW_DATA_ANDREJ     => raw_harris,
00417       RAW_DATA_HEINZ      => raw_helmut,
00418       COARSE_TIME_IRENA   => COARSE_TIME_WILLIAM,
00419       COARSE_TIME_EWA     => COARSE_TIME_MARKO,
00420       COARSE_TIME_ANDREJ  => COARSE_TIME_HARRIS,
00421       COARSE_TIME_HEINZ   => COARSE_TIME_HELMUT,
00422       ADJUST_TIME_IRENA   => ADJUST_TIME_WILLIAM,
00423       ADJUST_TIME_EWA     => ADJUST_TIME_MARKO,
00424       ADJUST_TIME_ANDREJ  => ADJUST_TIME_HARRIS,
00425       ADJUST_TIME_HEINZ   => ADJUST_TIME_HELMUT,
00426       ADJUST_TIME_IRENA2  => ADJUST_TIME_WILLIAM2,
00427       ADJUST_TIME_EWA2    => ADJUST_TIME_MARKO2,
00428       ADJUST_TIME_ANDREJ2 => ADJUST_TIME_HARRIS2,
00429       ADJUST_TIME_HEINZ2  => ADJUST_TIME_HELMUT2
00430       );
00431 
00432 
00433   side_c : side_4rios
00434     generic map (
00435       PATTERN => XOR_PAT)
00436     port map
00437     (
00438       BCLK                => BCLK,
00439       BCLK2X              => BCLK2X,
00440       BCLK4X              => BCLK4X,
00441       RIOCLK_1            => RIOCLK_1,
00442       RIOCLK_2            => RIOCLK_2,
00443       EN                  => EN,
00444       SET_SHIFT_1         => "00000000",
00445       SET_SHIFT_2         => "00000000",
00446       CAL                 => CALIBRATE_RIOS,
00447       CHECK_IRENA         => check5,
00448       CHECK_EWA           => check6,
00449       CHECK_ANDREJ        => check7,
00450       CHECK_HEINZ         => check8,
00451       RES                 => RESET,
00452       SEP_RES             => SEP_RESET(3 downto 0),
00453       TX_SYSTEM_RESET_IN  => '0',
00454       RX_SYSTEM_RESET_IN  => '0',
00455       RXLOCK_OUT_IRENA    => RX_LOCK2,
00456       TXLOCK_OUT_IRENA    => TX_LOCK2,
00457       RXLOCK_OUT_EWA      => RX_LOCK1,
00458       TXLOCK_OUT_EWA      => TX_LOCK1,
00459       RXLOCK_OUT_ANDREJ   => RX_LOCK4,
00460       TXLOCK_OUT_ANDREJ   => TX_LOCK4,
00461       RXLOCK_OUT_HEINZ    => RX_LOCK3,
00462       TXLOCK_OUT_HEINZ    => TX_LOCK3,
00463       RX1N_IN_IE          => RXN_C_IE,
00464       RX1P_IN_IE          => RXP_C_IE,
00465       TX1N_OUT_IE         => TXN_C_IE,
00466       TX1P_OUT_IE         => TXP_C_IE,
00467       RX1N_IN_AH          => RXN_C_AH,
00468       RX1P_IN_AH          => RXP_C_AH,
00469       TX1N_OUT_AH         => TXN_C_AH,
00470       TX1P_OUT_AH         => TXP_C_AH,
00471       RX_READY_FLAG_IE    => readyc1,
00472       TX_READY_FLAG_IE    => readyc2,
00473       RX_READY_FLAG_AH    => readyc3,
00474       TX_READY_FLAG_AH    => readyc4,
00475       SUM_RIS_IRENA       => mult_irena_i,
00476       SUM_FAL_IRENA       => open,
00477       T1_IRENA            => t1_irena_i,
00478       T2_IRENA            => t2_irena_i,
00479       T3_IRENA            => open,
00480       W1_IRENA            => w1_irena_i,
00481       W2_IRENA            => w2_irena_i,
00482       W3_IRENA            => open,
00483       STATUS_T1_IRENA     => irena_1,
00484       STATUS_T2_IRENA     => irena_2,
00485       STATUS_T3_IRENA     => open,
00486       STATUS_W1_IRENA     => open,
00487       STATUS_W2_IRENA     => open,
00488       STATUS_W3_IRENA     => open,
00489       OVERFLOW_IRENA      => open,
00490       SUM_RIS_EWA         => mult_ewa_i,
00491       SUM_FAL_EWA         => open,
00492       T1_EWA              => t1_ewa_i,
00493       T2_EWA              => t2_ewa_i,
00494       T3_EWA              => open,
00495       W1_EWA              => w1_ewa_i,
00496       W2_EWA              => w2_ewa_i,
00497       W3_EWA              => open,
00498       STATUS_T1_EWA       => ewa_1,
00499       STATUS_T2_EWA       => ewa_2,
00500       STATUS_T3_EWA       => open,
00501       STATUS_W1_EWA       => open,
00502       STATUS_W2_EWA       => open,
00503       STATUS_W3_EWA       => open,
00504       OVERFLOW_EWA        => open,
00505       SUM_RIS_ANDREJ      => mult_andrej_i,
00506       SUM_FAL_ANDREJ      => open,
00507       T1_ANDREJ           => t1_andrej_i,
00508       T2_ANDREJ           => t2_andrej_i,
00509       T3_ANDREJ           => open,
00510       W1_ANDREJ           => w1_andrej_i,
00511       W2_ANDREJ           => w2_andrej_i,
00512       W3_ANDREJ           => open,
00513       STATUS_T1_ANDREJ    => andrej_1,
00514       STATUS_T2_ANDREJ    => andrej_2,
00515       STATUS_T3_ANDREJ    => open,
00516       STATUS_W1_ANDREJ    => open,
00517       STATUS_W2_ANDREJ    => open,
00518       STATUS_W3_ANDREJ    => open,
00519       OVERFLOW_ANDREJ     => open,
00520       SUM_RIS_HEINZ       => mult_heinz_i,
00521       SUM_FAL_HEINZ       => open,
00522       T1_HEINZ            => t1_heinz_i,
00523       T2_HEINZ            => t2_heinz_i,
00524       T3_HEINZ            => open,
00525       W1_HEINZ            => w1_heinz_i,
00526       W2_HEINZ            => w2_heinz_i,
00527       W3_HEINZ            => open,
00528       STATUS_T1_HEINZ     => heinz_1,
00529       STATUS_T2_HEINZ     => heinz_2,
00530       STATUS_T3_HEINZ     => open,
00531       STATUS_W1_HEINZ     => open,
00532       STATUS_W2_HEINZ     => open,
00533       STATUS_W3_HEINZ     => open,
00534       OVERFLOW_HEINZ      => open,
00535       MASK_IRENA          => MASK_IRENA,
00536       MASK_EWA            => MASK_EWA,
00537       MASK_ANDREJ         => MASK_ANDREJ,
00538       MASK_HEINZ          => MASK_HEINZ,
00539       CAL_IRENA           => CAL_IRENA,
00540       CAL_EWA             => CAL_EWA,
00541       CAL_ANDREJ          => CAL_ANDREJ,
00542       CAL_HEINZ           => CAL_HEINZ,
00543       CAL_DONE            => done2,
00544       RAW_DATA_IRENA      => raw_irena,
00545       RAW_DATA_EWA        => raw_ewa ,
00546       RAW_DATA_ANDREJ     => raw_andrej,
00547       RAW_DATA_HEINZ      => raw_heinz,
00548       COARSE_TIME_IRENA   => COARSE_TIME_IRENA,
00549       COARSE_TIME_EWA     => COARSE_TIME_EWA,
00550       COARSE_TIME_ANDREJ  => COARSE_TIME_ANDREJ,
00551       COARSE_TIME_HEINZ   => COARSE_TIME_HEINZ,
00552       ADJUST_TIME_IRENA   => ADJUST_TIME_IRENA,
00553       ADJUST_TIME_EWA     => ADJUST_TIME_EWA,
00554       ADJUST_TIME_ANDREJ  => ADJUST_TIME_ANDREJ,
00555       ADJUST_TIME_HEINZ   => ADJUST_TIME_HEINZ,
00556       ADJUST_TIME_IRENA2  => ADJUST_TIME_IRENA2,
00557       ADJUST_TIME_EWA2    => ADJUST_TIME_EWA2,
00558       ADJUST_TIME_ANDREJ2 => ADJUST_TIME_ANDREJ2,
00559       ADJUST_TIME_HEINZ2  => ADJUST_TIME_HEINZ2
00560       );
00561 
00562 end rios_all_arc;
00563